ADN4668
Rev. A | Page 4 of 12
AC CHARACTERISTICS
V
DD
= 3.0 V to 3.6 V, C
L
= 15 pF to GND, all specifications T
MIN
to T
MAX
, unless otherwise noted.
1, 2, 3, 4
Table 2.
Parameter
5
Min Typ Max Unit Conditions/Comments
6
Differential Propagation Delay, High-to-Low, t
PHLD
1.2 2.0 2.7 ns C
L
= 15 pF,
7
V
ID
= 200 mV, see Figure 2 and Figure 3
Differential Propagation Delay, Low-to-High, t
PLHD
1.2 1.9 2.7 ns C
L
= 15 pF,
7
V
ID
= 200 mV, see Figure 2 and Figure 3
Differential Pulse Skew |t
PHLD
− t
PLHD
|, t
SKD1
8
0 0.1 0.4 ns C
L
= 15 pF,
7
V
ID
= 200 mV, see Figure 2 and Figure 3
Differential Channel-to-Channel Skew, Same Device, t
SKD2
3
0 0.15 0.5 ns C
L
= 15 pF,
7
V
ID
= 200 mV, see Figure 2 and Figure 3
Differential Part-to-Part Skew, t
SKD3
4
1.0 ns C
L
= 15 pF,
7
V
ID
= 200 mV, see Figure 2 and Figure 3
Differential Part-to-Part Skew, t
SKD4
9
1.5 ns C
L
= 15 pF,
7
V
ID
= 200 mV, see Figure 2 and Figure 3
Rise Time, t
TLH
0.5 1.0 ns C
L
= 15 pF,
7
V
ID
= 200 mV, see Figure 2 and Figure 3
Fall Time, t
THL
0.35 1.0 ns C
L
= 15 pF,
7
V
ID
= 200 mV, see Figure 2 and Figure 3
Disable Time, High-to-Z, t
PHZ
8 14 ns R
L
= 2 kΩ, C
L
= 15 pF,
7
see Figure 4 and Figure 5
Disable Time, Low-to-Z, t
PLZ
8 14 ns R
L
= 2 kΩ, C
L
= 15 pF,
7
see Figure 4 and Figure 5
Enable Time, Z-to-High, t
PZH
9 14 ns R
L
= 2 kΩ, C
L
= 15 pF,
7
see Figure 4 and Figure 5
Enable Time, Z-to-Low, t
PZL
9 14 ns R
L
= 2 kΩ, C
L
= 15 pF,
7
see Figure 4 and Figure 5
Maximum Operating Frequency, f
MAX
10
200 250 MHz All channels switching
1
All typicals are given for V
CC
= 3.3 V and T
A
= 25°C.
2
Generator waveform for all tests, unless otherwise specified: f = 1 MHz, Z
O
= 50 Ω, and t
R
and t
F
(0% to 100%) ≤ 3 ns for R
INx+
/R
INx−
.
3
Channel-to-channel skew, t
SKD2
, is defined as the difference between the propagation delay of one channel and that of the others on the same chip with any event on
the inputs.
4
Part-to-part skew, t
SKD3
, is the differential channel-to-channel skew of any event between devices. This specification applies to devices at the same V
CC
and within 5°C of
each other within the operating temperature range.
5
AC parameters are guaranteed by design and characterization.
6
Current-into-device pins are defined as positive. Current-out-of-device pins are defined as negative. All voltages are referenced to ground, unless otherwise specified.
7
C
L
includes probe and jig capacitance.
8
t
SKD1
is the magnitude difference in the differential propagation delay time between the positive-going edge and the negative-going edge of the same channel.
9
Part-to-part skew, t
SKD4
, is the differential channel-to-channel skew of any event between devices. This specification applies to devices over the recommended
operating temperature and voltage ranges and across process distribution. t
SKD4
is defined as |maximum − minimum| differential propagation delay.
10
f
MAX
generator input conditions: f = 200 MHz, t
R
= t
F
< 1 ns (0% to 100%), 50% duty cycle, differential (1.05 V p-p to 1.35 V p-p). Output criteria: 60%/40% duty cycle,
V
OL
(maximum = 0.4 V), V
OH
(minimum = 2.7 V), C
L
= 15 pF (stray plus probes).
TEST CIRCUITS AND WAVEFORMS
SIGNAL
GENERATOR
RECEIVER
IS ENABLED
R
INx+
R
INx–
C
L
C
L
= LOAD AND TEST JIG CAPACITANCE
CC
R
OUTx
50Ω 50Ω
07237-002
Figure 2. Test Circuit for Receiver Propagation Delay and Transition Time
80%80%
20%
1.5V
20%
1.5V
t
PLHD
t
PHLD
R
INx–
R
INx+
0V (DIFFERENTIAL)
t
TLH
t
THL
V
OH
V
OL
1.2V
1.3V
1.1V
R
OUTx
V
ID
= 200mV
07237-003
Figure 3. Receiver Propagation Delay and Transition Time Waveforms
