FEMTOCLOCK
®
CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR 10 REVISION B 10/15/15
843051 DATA SHEET
Termination for 3.3V LVPECL Outputs
The clock layout topology shown below is a typical termination for
LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
The differential outputs are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must be
used for functionality. These outputs are designed to drive 50
transmission lines. Matched impedance techniques should be used
to maximize operating frequency and minimize signal distortion.
Figures 4A and 4B show two different layouts which are
recommended only as guidelines. Other suitable clock layouts may
exist and it would be recommended that the board designers
simulate to guarantee compatibility across all printed circuit and clock
component process variations.
Figure 4A. 3.3V LVPECL Output Termination Figure 4B. 3.3V LVPECL Output Termination
R1
84
R2
84
3.3V
R3
125
R4
125
Z
o
= 50
Z
o
= 50
Input
3.3V
3.3V
+
_
REVISION B 10/15/15 11 FEMTOCLOCK
®
CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR
843051 DATA SHEET
Schematic Example
Figure 5A shows a schematic example of the 843051. An example of
LVEPCL termination is shown in this schematic. Additional LVPECL
termination approaches are shown in the LVPECL Termination
Application Note. In this example, an 18pF parallel resonant crystal
is used. The C1 = 27pF and C2 = 33pF are recommended for
frequency accuracy. The C1 and C2 values may be slightly adjusted
for optimizing frequency accuracy.
Figure 5A. 843051 Schematic Example
PC Board Layout Example
Figure 5B shows an example of 843051 P.C. board layout. The crystal
X1 footprint shown in this example allows installation of either surface
mount HC49S or through-hole HC49 package. The footprints of other
components in this example are listed in the Ta b l e 6 . There should be
at least one decoupling capacitor per power pin. The decoupling
capacitors should be located as close as possible to the power pins.
The layout assumes that the board has clean analog power ground
plane.
Figure 5B. 843051 PC Board Layout Example Table 6. Footprint Table
NOTE: Table 6 lists component sizes shown in this layout example.
R4
82.5
R1
1K
C4
0.01u
VCC
+
-
VCC
Zo = 50 Ohm
R6
82.5
C1
27pF
C3
10uF
Zo = 50 Ohm
C2
33pF
R2
10
VCC
R3
133
U1
ICS843051i
1
2
3
4
8
7
6
5
VCCA
VEE
XTA L_ O U T
XTA L_ I N
VCC
Q0
nQ0
FREQ_SEL
C5
0.1u
Q
VCCA
R5
133
VCC
nQ
X119.44MHz
Reference Size
C1, C2 0402
C3 0805
C4, C5 0603
R2 0603
FEMTOCLOCK
®
CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR 12 REVISION B 10/15/15
843051 DATA SHEET
Power Considerations
This section provides information on power dissipation and junction temperature for the 843051.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the 843051 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V
CC
= 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
Power (core)
MAX
= V
CC_MAX
* I
EE_MAX
= 3.465V * 85mA = 294.5mW
Power (outputs)
MAX
= 30mW/Loaded Output pair
Total Power_
MAX
(3.465V, with all outputs switching) = 294.5mW + 30mW = 324.5mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj =
JA
* Pd_total + T
A
Tj = Junction Temperature
JA
= Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T
A
= Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance
JA
must be used. Assuming a moderate air
flow of 1 meter per second and a multi-layer board, the appropriate value is 90.5°C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.324W * 90.5°C/W = 99.3°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 7. Thermal Resitance
JA
for 8 Lead TSSOP, Forced Convection
JA
vs. Air Flow
Meters per Second 012.5
Multi-Layer PCB, JEDEC Standard Test Boards 101.7°C/W 90.5°C/W 89.8°C/W

843051AGLF

Mfr. #:
Manufacturer:
IDT
Description:
Clock Generators & Support Products FemtoClock Crystal Crystal-to-3.3V
Lifecycle:
New from this manufacturer.
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