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ATA6839-PXQW

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18
4
4955D–AUTO–10/08
ATA6839 [Preliminary]
17 CS
Chip select input; 5V CMOS logic level input with internal pull up;
low = serial communication is enabled, high = disabled
18 CLK
Serial clock input; 5V CMOS logic level input with internal pull down;
controls serial data input interface and internal shift register (f
max
= 2 MHz)
19 DI
Serial data input; 5V CMOS logic level input with internal pull down; receives serial data from the control
device; DI expects a 16-bit control word with LSB being transferred first
20 OUT6 Output 6; see pin 1
21 OUT6 SENSE Only for testability in final test
22 OUT5 SENSE Only for testability in final test
23 OUT5 Output 5; see pin 1
24 NC Internal bond to GND
Table 2-1. Pin Description QFN24 (Continued)
Pin Symbol Function
5
4955D–AUTO–10/08
ATA6839 [Preliminary]
3. Functional Description
3.1 Serial Interface
Data transfer starts with the falling edge of the CS signal. Data must appear at DI synchronized
to CLK and is accepted on the falling edge of the CLK signal. LSB (bit 0, SRR) has to be trans-
ferred first. Execution of new input data is enabled on the rising edge of the CS signal. When CS
is high, pin DO is in a tri-state condition. This output is enabled on the falling edge of CS. Output
data will change their state with the rising edge of CLK and stay stable until the next rising edge
of CLK appears. LSB (bit 0, TP) is transferred first.
Figure 3-1. Data Transfer Input Data Protocol
SRR LS1 HS1 LS2 HS2 LS3
HS3
LS4
HS4 LS5 HS5 LS6 HS6
OLD
SCT SI
CS
DI
CLK
DO
TP SLS1 SHS1 SLS2 SHS2 SLS3 SHS3 SLS4
SHS4 SLS5 SHS5 SLS6 SHS6 SCD INH PSF
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Table 3-1. Input Data Protocol
Bit Input Register Function
0SRR
Status register reset (high = reset; the bits PSF, SCD and
overtemperature shutdown in the output data register are set to low)
1 LS1 Controls output LS1 (high = switch output LS1 on)
2 HS1 Controls output HS1 (high = switch output HS1 on)
3 LS2 See LS1
4 HS2 See HS1
5 LS3 See LS1
6 HS3 See HS1
7 LS4 See LS1
8 HS4 See HS1
9 LS5 See LS1
10 HS5 See HS1
11 LS6 See LS1
12 HS6 See HS1
13 OLD Open load detection (low = on)
14 SCT
Programmable time delay for short circuit
(shutdown delay high/low = 12 ms/1.5 ms)
15 SI
Software inhibit; low = standby, high = normal operation
(data transfer is not affected by standby function because the digital
part is still powered)
6
4955D–AUTO–10/08
ATA6839 [Preliminary]
Table 3-2. Output Data Protocol
Bit
Output (Status)
Register Function
0TP
Temperature prewarning: high = warning
(overtemperature shutdown see remark below)
1 Status LS1
Normal operation: high = output is on, low = output is off
Open-load detection: high = open load, low = no open load
(correct load condition is detected if the corresponding output is
switched off)
2 Status HS1
Normal operation: high = output is on, low = output is off
Open-load detection: high = open load, low = no open load
(correct load condition is detected if the corresponding output is
switched off)
3 Status LS2 Description see LS1
4 Status HS2 Description see HS1
5 Status LS3 Description see LS1
6 Status HS3 Description see HS1
7 Status LS4 Description see LS1
8 Status HS4 Description see HS1
9 Status LS5 Description see LS1
10 Status HS5 Description see HS1
11 Status LS6 Description see LS1
12 Status HS6 Description see HS1
13 SCD
Short circuit detected: set high, when at least one output is switched off
by a short circuit condition
14 INH
Inhibit: this bit is controlled by software (bit SI in input register) and
hardware inhibit (pin INH). High = standby, low = normal operation
15 PSF Power supply fail: undervoltage at pin VS detected
Note: Bit 0 to 15 = high: overtemperature shutdown
Table 3-3. Status of the Input Register After Power on Reset
Bit 15
(SI)
Bit 14
(SCT)
Bit 13
(OLD)
Bit 12
(HS6)
Bit 11
(LS6)
Bit 10
(HS5)
Bit 9
(LS5)
Bit 8
(HS4)
Bit 7
(LS4)
Bit 6
(HS3)
Bit 5
(LS3)
Bit 4
(HS2)
Bit 3
(LS2)
Bit 2
(HS1)
Bit 1
(LS1)
Bit 0
(SRR)
HHHLLLLLLLLLLLLL
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18

ATA6839-PXQW

Mfr. #:
Buy ATA6839-PXQW
Manufacturer:
Microchip Technology / Atmel
Description:
Gate Drivers 1A 5A Hex Half Bridge Driver
Lifecycle:
New from this manufacturer.
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