13
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V
CCA
/V
CCB
undervoltage faults are determined by compar-
ing the actual output voltage with the internal reference
voltage. If the output is more than ~5% below its set point
for the entire timeout period, the fault is reported and the
deactivation sequence is initiated.
V
CCA
/V
CCB
overcurrent faults are detected by comparing
the output current of the LDOs with an internal reference
level. If the current of an LDO is more than 100mA (typ)
for the entire timeout period, the fault is reported and the
deactivation sequence is initiated.
CLK A/CLK B and RST A/RST B faults are detected by
comparing the outputs of these pins with their expected
signals. If the signal on a pin is incorrect for the entire
timeout period, the fault is reported and the deactivation
sequence is initiated.
The clock channels are a special case. Since they can have
a free running clock, the error indication is accumulated
over a longer period of time without being cleared. Even
though the clock may be running, an error will still be
detected.
An overtemperature fault is detected by sensing the junction
temperature of the IC. If the junction temperature exceeds
approximately 150°C for the entire timeout period, the
fault is reported by setting both fault bits (D4 and D12)
and the deactivation sequence is initiated.
A card removal fault is determined as soon as the PRES A/
PRES B pin is high (for NC/NO = 0). Once this occurs,
the fault is reported and the deactivation sequence is
initiated.
If no card is present, and the application software attempts
to power-up a card socket, an automatic fault will result
on that channel.
Short-circuits on the I/O A/I/O B lines will not be detected
by the fault detection hardware; however, a short-circuit
from these lines to their respective V
CCA
/V
CCB
pins will
be compliant with the maximum current limits set by ap-
plicable standards (<15mA).
An
electrical fault can be cleared on either channel by
setting the voltage of that channel to 0V. Set D0 and D1
to
OO to clear channel B and set D8 and D9 to 00 to clear
channel A. It is not necessary to set all four bits to zeros.
Answer to Reset (ATR) Fault Detection
Answer to reset faults are detected by an internal counter
that is started once the RST A/B line goes high. If the DATA
pin remains high for 40,000 clock cycles, the ATR fault bit
for a given channel is set in the serial port’s status register
(see Table 1) and the FAULT pin is brought low.
An ATR fault cannot occur if the clock mode of a chan
-
nel is set to synchronous. ATR faults will only occur for
asynchronous smart cards.
A
TR faults are cleared by bringing the RST A/B pin low
for the faulted channel. This will also clear the FAULT pin
to the Hi-Z state (assuming no other errors are causing
FAULT to be low).
An ATR fault will not automatically deactivate a card
channel. It is the application programmer’s responsibility
to check the status register for ATR faults and deacti
-
vate the smart card channel in accordance with smart
card standards. Generally, the application has 50ms
(EMV 2.1.3.1, 2.1.3.2) from the 40,000th clock pulse to
deactivate the card. Once the LTC1955 receives the de-
activation command, it will shut down a card channel in
less than 250µs.
Using the
FAULT Pin
The FAULT pin can be used as an interrupt to a microcon
-
troller. It is an open-drain output and generally requires
a pull-up resistor
. The FAULT pin will go low when either
an electrical fault, or an answer to reset fault, occurs on
either channel. Thus, there are four possible faults that
can cause it to indicate a problem. The serial port’s status
register must be polled to find out what type of fault oc
-
curred and on which channel. The FAULT pin is logically
equivalent to D4 + D5 + D12 + D13 (see Table 1).
operaTion
