MT40A2G8FSE-093E:A TR Datasheet MT40A2G8FSE-093E:A TR, MT40A2G8FSE-083E:A, MT40A2G8FSE-083E:A TR | P4-P6

Table 3: FBGA 78-Ball Descriptions

Symbol Type Description

A[17:0] Input Address inputs: Provide the row address for ACTIVATE commands and the col-

umn address for READ/WRITE commands to select one location out of the memo-

ry array in the respective bank. (A10/AP, A12/BC_n, WE_n/A14, CAS_n/A15, RAS_n/

A16, have additional functions; see individual entries in this table). The address

inputs also provide the op-code during the MODE REGISTER SET command. A16 is

used on some 8Gb and 16Gb parts, and A17 is only used on some 16Gb parts.

A10/AP Input Auto precharge: A10 is sampled during READ and WRITE commands to deter-

mine whether auto precharge should be performed to the accessed bank after a

READ or WRITE operation (HIGH = auto precharge; LOW = no auto precharge).

A10 is sampled during a PRECHARGE command to determine whether the PRE-

CHARGE applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one

bank is to be precharged, the bank is selected by the bank group and bank ad-

dresses.

A12/BC_n Input Burst chop: A12/BC_n is sampled during READ and WRITE commands to deter-

mine if burst chop (on-the-fly) will be performed. (HIGH = no burst chop; LOW =

burst-chopped). See the Command Truth Table.

ACT_n Input Command input: ACT_n indicates an ACTIVATE command. When ACT_n (along

with CS_n) is LOW, the input pins RAS_n/A16, CAS_n/A15, and WE_n/A14 are trea-

ted as row address inputs for the ACTIVATE command. When ACT_n is HIGH

(along with CS_n LOW), the input pins RAS_n/ A16, CAS_n/A15, and WE_n/A14

are treated as normal commands that use the RAS_n, CAS_n, and WE_n signals.

See the Command Truth Table.

BA[1:0] Input Bank address inputs: Define the bank (within a bank group) to which an ACTI-

VATE, READ, WRITE, or PRECHARGE command is being applied. Also determines

which mode register is to be accessed during a MODE REGISTER SET command.

BG[1:0] Input Bank group address inputs: Define the bank group to which a REFRESH, ACTI-

VATE, READ, WRITE, or PRECHARGE command is being applied. Also determines

which mode register is to be accessed during a MODE REGISTER SET command.

BG[1:0] are used in the x4 and x8 configurations.

C0/CKE1,

C1/CS1_n,

C2/ODT1

Input Stack address inputs: These inputs are used only when devices are stacked;

that is, 2H, 4H, and 8H stacks for x4 and x8 configurations (these pins are not

used in the x16 configuration). DDR4 will support a traditional dual-die package

(DDP), which uses these three signals for control of the second die (CS1_n, CKE1,

ODT1). DDR4 is not expected to support a traditional quad-die package (QDP).

For all other stack configurations, such as a 4H or 8H, it is assumed to be a single-

load (master/slave) type of configuration where C0, C1, and C2 are used as chip

ID selects in conjunction with a single CS_n, CKE, and ODT.

CK_t,

CK_c

Input Clock: Differential clock inputs. All address, command, and control input signals

are sampled on the crossing of the positive edge of CK_t and the negative edge

of CK_c.

16Gb: x4, x8 TwinDie DDR4 SDRAM

Ball Assignments and Descriptions

PDF: 09005aef85fd40a1

DDR4_16Gb_x4_x8_2CS_TwinDie.pdf - Rev. D 12/16 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

Table 3: FBGA 78-Ball Descriptions (Continued)

Symbol Type Description

CKE Input Clock enable: CKE HIGH activates, and CKE LOW deactivates, the internal clock

signals, device input buffers, and output drivers. Taking CKE LOW provides PRE-

CHARGE POWER-DOWN and SELF REFRESH operations (all banks idle), or active

power-down (row active in any bank). CKE is asynchronous for self refresh exit.

After V

REFCA

has become stable during the power-on and initialization sequence,

it must be maintained during all operations (including SELF REFRESH). CKE must

be maintained HIGH throughout read and write accesses. Input buffers (exclud-

ing CK_t, CK_c, ODT, RESET_n, and CKE are disabled during power-down. Input

buffers (excluding CKE and RESET#) are disabled during self refresh.

CS_n Input Chip select: All commands are masked when CS_n is registered HIGH. CS_n pro-

vides for external rank selection on systems with multiple ranks. CS_n is consid-

ered part of the command code.

DM_nS Input Input data mask: DM_n is an input mask signal for write data. Input data is

masked when DM is sampled LOW coincident with that input data during a write

access. DM is sampled on both edges of DQS. DM is not supported on x4 configu-

rations. LDM_n is associated with DQ[7:0]. The DM, DBI, and TDQS functions are

enabled by mode register settings. See the Data Mask (DM) section.

ODT Input On-die termination: ODT (registered HIGH) enables termination resistance in-

ternal to the DDR4 SDRAM. When enabled, ODT (R

) is applied only to each DQ,

DQS_t, DQS_c, DM_n/DBI_n/TDQS_t, and TDQS_c signal for the x4 and x8 configu-

rations (when the TDQS function is enabled via mode register). The ODT pin will

be ignored if the mode registers are programmed to disable R

PAR Input Parity for command and address: This function can be enabled or disabled via

the mode register. When enabled, the parity signal covers all command and ad-

dress inputs, including RAS_n/A16, CAS_n/A15, WE_n/A14, A[17:0], A10/AP, A12/

BC_n, BA[1:0], BG[1:0], C0/A18, C1/A19, C2/A20. Control pins NOT covered by the

parity signal are CS_n, CKE, and ODT. Unused address pins that are density- and

configuration-specific should be treated internally as 0s by the DRAM parity log-

ic.

RAS_n/A16,

CAS_n/A15,

WE_n/A14

Input Command inputs: RAS_n/A16 , CAS_n/A15, and WE_n/A14 (along with CS_n and

ACT_n) define the command and/or address being entered. See the ACT_n de-

scription in this table.

RESET_n Input Active LOW asynchronous reset: Reset is active when RESET_n is LOW, and in-

active when RESET_n is HIGH. RESET_n must be HIGH during normal operation.

RESET_n is a CMOS rail-to-rail signal with DC HIGH and LOW at 80% and 20% of

; that is, 960 mV for DC HIGH and 240 mV for DC LOW.

TEN Input Connectivity test mode: TEN is active when HIGH and inactive when LOW. TEN

must be LOW during normal operation. TEN is a CMOS rail-to-rail signal with DC

HIGH and LOW at 80% and 20% of V

(960mV for DC HIGH and 240mV for DC

LOW).

16Gb: x4, x8 TwinDie DDR4 SDRAM

Ball Assignments and Descriptions

PDF: 09005aef85fd40a1

DDR4_16Gb_x4_x8_2CS_TwinDie.pdf - Rev. D 12/16 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

Table 3: FBGA 78-Ball Descriptions (Continued)

Symbol Type Description

DQ I/O Data input/output: Bidirectional data bus. DQ represents DQ[3:0], and DQ[7:0]

for the x4, and x8, respectively. If write CRC is enabled via mode register, the

write CRC code is added at the end of data burst. Any one or all of DQ0, DQ1,

DQ2, and DQ3 may be used to monitor the internal V

REF

level during test via

mode register setting MR[4] A[4] = HIGH, training times change when enabled.

During this mode, R

value should be set to High-Z. This measurement is for veri-

fication purposes and is NOT an external voltage supply pin.

DBI_n I/O DBI input/output: Data bus inversion. DBI_n is an input/output signal used for

data bus inversion in the x8 configuration. DBI_n is associated with DQ[7:0]. The

DBI feature is not supported on x4 configurations. DBI can be configured for

both READ (output) and WRITE (input) operations depending on the mode regis-

ter settings. The DM, DBI, and TDQS functions are enabled by mode register set-

tings. See the Data Bus Inversion (DBI) section.

DQS_t,

DQS_c

I/O Data strobe: Output with READ data, input with WRITE data. Edge-aligned with

READ data, centered-aligned with WRITE data. For the x4 and x8 configurations,

DQS corresponds to the data on DQ[3:0] and DQ[7:0] respectively. DDR4 SDRAM

supports a differential data strobe only and does not support a single-ended data

strobe.

ALERT_n Output Alert output: This signal allows the DRAM to indicate to the system's memory

controller that a specific alert or event has occurred. Alerts will include the com-

mand/address parity error and the CRC data error when either of these functions

is enabled in the mode register.

TDQS_t,

TDQS_c

Output Termination data strobe: TDQS_t and TDQS_c are used by x8 DRAMs only.

When enabled via the mode register, the DRAM will enable the same R

termi-

nation resistance on TDQS_t and TDQS_c that is applied to DQS_t and DQS_c.

When the TDQS function is disabled via the mode register, the DM/TDQS_t pin

will provide the data mask (DM) function, and the TDQS_c pin is not used. The

TDQS function must be disabled in the mode register for the x4 configuration.

The DM function is supported only in x8 configuration.

Supply Power supply: 1.2V ±0.060V.

DDQ

Supply DQ power supply: 1.2V ±0.060V.

Supply DRAM activating power supply: 2.5V -0.125V / +0.250V.

REFCA

Supply Reference voltage for control, command, and address pins.

Supply Ground.

SSQ

Supply DQ ground.

ZQ Reference Reference ball for ZQ calibration: This ball is tied to an external 240Ω resistor

(RZQ), which is tied to V

SSQ

. Note that this ball is shared by two DRAM devices. As

a result, ZQ calibration operations need to be carried out separately so that cor-

rect values are achieved.

RFU – Reserved for future use.

NC – No connect: No internal electrical connection is present.

NF – No function: May have internal connection present, but has no function.

16Gb: x4, x8 TwinDie DDR4 SDRAM

Ball Assignments and Descriptions

PDF: 09005aef85fd40a1

DDR4_16Gb_x4_x8_2CS_TwinDie.pdf - Rev. D 12/16 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

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