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74ALVC374PW,118

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18
74ALVC374_2 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 02 — 17 October 2007 9 of 17
NXP Semiconductors
74ALVC374
Octal D-type flip-flop; positive-edge trigger; 3-state
11. Waveforms
Measurement points are given in Table 8.
V
OL
and V
OH
are the typical output voltage levels that occur with the output load.
Fig 7. Clock (CP) to output (Qn) propagation delays, the clock pulse width and the maximum frequency
mna894
CP
input
Qn
output
t
PHL
t
PLH
t
W
1/f
max
V
M
V
OH
V
I
GND
V
OL
V
M
Table 8. Measurement points
Supply voltage Input Output
V
CC
V
M
V
M
V
x
V
y
1.65 V to 1.95 V 0.5V
CC
0.5V
CC
V
OL
+ 0.15 V V
OH
− 0.15 V
2.3 V to 2.7 V 0.5V
CC
0.5V
CC
V
OL
+ 0.15 V V
OH
− 0.15 V
2.7 V 2.7 V 1.5 V V
OL
+ 0.3 V V
OH
− 0.3 V
3.0 V to 3.6 V 2.7 V 1.5 V V
OL
+ 0.3 V V
OH
− 0.3 V
Measurement points are given in Table 8.
V
OL
and V
OH
are the typical output voltage drops that occur with the output load.
Fig 8. Enable and disable times
mna644
t
PLZ
t
PHZ
outputs
disabled
outputs
enabled
V
Y
V
X
outputs
enabled
output
LOW-to-OFF
OFF-to-LOW
output
HIGH-to-OFF
OFF-to-HIGH
OE input
V
I
V
OL
V
OH
V
CC
V
M
GND
GND
t
PZL
t
PZH
V
M
V
M
74ALVC374_2 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 02 — 17 October 2007 10 of 17
NXP Semiconductors
74ALVC374
Octal D-type flip-flop; positive-edge trigger; 3-state
Measurement points are given in Table 8.
V
OL
and V
OH
are the typical output voltage drops that occur with the output load.
The shaded areas indicate when the input is permitted to change for predicable output performance.
Fig 9. Data set-up and hold times for the Dn input to the CP input
mna202
GND
GND
t
h
t
h
t
su
t
su
V
M
V
M
V
M
V
I
V
OH
V
OL
V
I
Qn output
CP input
Dn input
74ALVC374_2 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 02 — 17 October 2007 11 of 17
NXP Semiconductors
74ALVC374
Octal D-type flip-flop; positive-edge trigger; 3-state
Test data is given in Table 9.
Definitions for test circuit:
R
L
= Load resistance.
C
L
= Load capacitance including jig and probe capacitance.
R
T
= Termination resistance should be equal to output impedance Z
o
of the pulse generator.
V
EXT
= External voltage for measuring switching times.
Fig 10. Test circuitry for switching times
V
M
V
M
t
W
t
W
10 %
90 %
0 V
V
I
V
I
negative
pulse
positive
pulse
0 V
V
M
V
M
90 %
10 %
t
f
t
r
t
r
t
f
001aae331
V
EXT
V
CC
V
I
V
O
DUT
C
L
R
T
R
L
R
L
G
Table 9. Test data
Supply voltage Input Load V
EXT
V
I
t
r
, t
f
C
L
R
L
t
PLH
, t
PHL
t
PLZ
, t
PZL
t
PHZ
, t
PZH
1.65 V to 1.95 V V
CC
≤ 2.0 ns 30 pF 1 kΩ open 2V
CC
GND
2.3 V to 2.7 V V
CC
≤ 2.0 ns 30 pF 500 Ω open 2V
CC
GND
2.7 V 2.7 V ≤ 2.5 ns 50 pF 500 Ω open 6 V GND
3.0 V to 3.6 V 2.7 V ≤ 2.5 ns 50 pF 500 Ω open 6 V GND
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18

74ALVC374PW,118

Mfr. #:
Buy 74ALVC374PW,118
Manufacturer:
Nexperia
Description:
Flip Flops 3.3V D-TYPE +EDGE
Lifecycle:
New from this manufacturer.
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