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74HCT191N,652

P1-P3P4-P6P7-P9P10-P12P13-P14
December 1990 7
Philips Semiconductors Product specification
Presettable synchronous 4-bit binary
up/down counter
74HC/HCT191
Fig.8 Typical load, count and
inhibit sequence.
Sequence
Load (preset) to binary thirteen;
count up to fourteen, fifteen,
zero, one and two;
inhibit;
count down to one, zero, fifteen,
fourteen and thirteen.
Fig.9 Logic diagram.
December 1990 8
Philips Semiconductors Product specification
Presettable synchronous 4-bit binary
up/down counter
74HC/HCT191
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
.
Output capability: standard
I
CC
category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; t
r
=t
f
= 6 ns; C
L
=50pF
SYMBOL PARAMETER
T
amb
(°C)
UNIT
TEST CONDITIONS
74HC
V
CC
(V)
WAVEFORMS
+25 −40 to +85 −40 to +125
min. typ. max. min. max. min. max.
t
PHL
/ t
PLH
propagation delay
CP to Q
n
72
26
21
220
44
37
275
55
47
330
66
56
ns 2.0
4.5
6.0
Fig.10
t
PHL
/ t
PLH
propagation delay
CP to TC
83
30
24
255
51
43
320
64
54
395
77
65
ns 2.0
4.5
6.0
Fig.10
t
PHL
/ t
PLH
propagation delay
CP to RC
47
17
14
150
30
26
190
38
33
225
45
38
ns 2.0
4.5
6.0
Fig.11
t
PHL
/ t
PLH
propagation delay
CE to RC
33
12
10
130
26
22
165
33
28
195
39
33
ns 2.0
4.5
6.0
Fig.11
t
PHL
/ t
PLH
propagation delay
D
n
to Q
n
61
22
18
220
44
37
275
55
47
330
66
56
ns 2.0
4.5
6.0
Fig.12
t
PHL
/ t
PLH
propagation delay
PL to Q
n
61
22
18
220
44
37
275
55
47
330
66
56
ns 2.0
4.5
6.0
Fig.13
t
PHL
/ t
PLH
propagation delay
U/D to TC
44
16
13
190
38
32
240
48
41
285
57
48
ns 2.0
4.5
6.0
Fig.14
t
PHL
/ t
PLH
propagation delay
U/D to RC
50
18
14
210
42
36
265
53
45
315
63
54
ns 2.0
4.5
6.0
Fig.14
t
THL
/ t
TLH
output transition time 19
7
6
75
15
13
95
19
16
110
22
19
ns 2.0
4.5
6.0
Fig.15
t
W
clock pulse width
HIGH or LOW
125
25
21
28
10
8
155
31
26
195
39
33
ns 2.0
4.5
6.0
Fig.10
t
W
parallel load pulse width
LOW
100
20
17
22
8
6
125
25
21
150
30
26
ns 2.0
4.5
6.0
Fig.15
December 1990 9
Philips Semiconductors Product specification
Presettable synchronous 4-bit binary
up/down counter
74HC/HCT191
t
rem
removal time
PL to CP
35
7
6
8
3
2
45
9
8
55
11
9
ns 2.0
4.5
6.0
Fig.15
t
su
set-up time
U/D to CP
205
41
35
50
18
14
255
51
43
310
62
53
ns 2.0
4.5
6.0
Fig.17
t
su
set-up time
D
n
to PL
100
20
17
19
7
6
125
25
21
150
30
26
ns 2.0
4.5
6.0
Fig.16
t
su
set-up time
CE to CP
140
28
24
44
16
13
175
35
30
210
42
36
ns 2.0
4.5
6.0
Fig.17
t
h
hold time
U/D to CP
0
0
0
−39
−14
−11
0
0
0
0
0
0
ns 2.0
4.5
6.0
Fig.17
t
h
hold time
D
n
to PL
0
0
0
−11
−4
−3
0
0
0
0
0
0
ns 2.0
4.5
6.0
Fig.16
t
h
hold time
CE to CP
0
0
0
−28
−10
−8
0
0
0
0
0
0
ns 2.0
4.5
6.0
Fig.17
f
max
maximum clock pulse
frequency
4.0
20
24
11
33
39
3.2
16
19
2.6
13
15
MHz 2.0
4.5
6.0
Fig.10
SYMBOL PARAMETER
T
amb
(°C)
UNIT
TEST CONDITIONS
74HC
V
CC
(V)
WAVEFORMS
+25 −40 to +85 −40 to +125
min. typ. max. min. max. min. max.
P1-P3P4-P6P7-P9P10-P12P13-P14

74HCT191N,652

Mfr. #:
Buy 74HCT191N,652
Manufacturer:
NXP Semiconductors
Description:
Counter ICs SYNC BIN U/D COUNTER
Lifecycle:
New from this manufacturer.
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