DS1338U-3 Datasheet DS1338C-18#, DS1338C-33#, DS1338C-3# | P7-P9

DS1338 I

C RTC with 56-Byte NV RAM

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PIN DESCRIPTION

NAME FUNCTION

1 — X1

32.768kHz Crystal Connections. The internal oscillator circuitry is designed for

operation with a crystal having a specified load capacitance (C

) of 12.5pF. An

external 32.768kHz oscillator can also drive the DS1338. In this configuration,

the X1 pin is connected to the external oscillator signal and the X2 pin is left

unconnected.

Note: For more information about crystal selection and crystal layout considerations,

refer to Application Note 58: Crystal Considerations with Dallas Real-Time Clocks.

2 — X2

3 14 V

BAT

Backup Supply Input for Lithium Cell or Other Energy Source. Battery voltage

must be held between the minimum and maximum limits for proper operation.

Diodes placed in series between the backup source and the V

BAT

pin may

prevent proper operation. If a backup supply is not required, V

BAT

must be

grounded. UL recognized to ensure against reverse charging when used with a

lithium cell. For more information, visit www.maxim-ic.com/qa/info/ul.

4 15 GND

Ground. DC power is provided to the device on these pins. V

is the primary

power input. When voltage is applied within normal limits, the device is fully

accessible and data can be written and read. When a backup supply is

connected to the device and V

is below V

, reads and writes are inhibited.

However, the timekeeping function continues unaffected by the lower input

voltage.

5 16 SDA

Serial Data. Input/output pin for the I

C serial interface. It is an open drain

output and requires an external pullup resistor. The pull up voltage may be up

to 5.5V regardless of the voltage on V

6 1 SCL

Serial Clock. Input pin for the I

C serial interface. Used to synchronize data

movement on the serial interface. The pull up voltage may be up to 5.5V

regardless of the voltage on V

7 2 SQW/OUT

Square-Wave/Output Driver. When enabled and the SQWE bit set to 1, the

SQW/OUT pin outputs one of four square-wave frequencies (1Hz, 4kHz, 8kHz,

32kHz). It is an open drain output and requires an external pullup resistor.

Operates with either V

or V

BAT

applied. The pull up voltage may be up to

5.5V regardless of the voltage on V

. If not used, this pin may be left

unconnected.

8 3 V

Primary Power Supply. When voltage is applied within normal limits, the device

is fully accessible and data can be written and read. When a backup supply is

connected to the device and V

is below V

, reads and writes are inhibited.

The backup supply maintains the timekeeping function while V

is absent.

— 4–13 N.C.

No Connection. These pins are not connected internally, but must be grounded

for proper operation.

DETAILED DESCRIPTION

The DS1338 serial RTC is a low-power, full BCD clock/calendar plus 56 bytes of NV SRAM. Address and data are

transferred serially through an I

C interface. The clock/calendar provides seconds, minutes, hours, day, date,

month, and year information. The end of the month date is automatically adjusted for months with fewer than 31

days, including corrections for leap year. The clock operates in either the 24-hour or 12-hour format with AM/PM

indicator. The DS1338 has a built-in power-sense circuit that detects power failures and automatically switches to

the V

BAT

supply.

DS1338 I

C RTC with 56-Byte NV RAM

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OPERATION

The DS1338 operates as a slave device on the serial bus. Access is obtained by implementing a START condition

and providing a device identification code, followed by data. Subsequent registers can be accessed sequentially

until a STOP condition is executed. The device is fully accessible and data can be written and read when V

greater than V

. However, when V

falls below V

, the internal clock registers are blocked from any access. If

is less than V

BAT

, the device power is switched from V

to V

BAT

when V

drops below V

. If V

is greater

than V

BAT

, the device power is switched from V

to V

BAT

when V

drops below V

BAT

. The oscillator and

timekeeping functions are maintained from the V

BAT

source until V

is returned to nominal levels. The block

diagram (Figure 3) shows the main elements of the DS1338.

An enable bit in the seconds register controls the oscillator. Oscillator startup times are highly dependent upon

crystal characteristics, PC board leakage, and layout. High ESR and excessive capacitive loads are the major

contributors to long start-up times. A circuit using a crystal with the recommended characteristics and proper layout

usually starts within 1 second.

POWER CONTROL

The power-control function is provided by a precise, temperature-compensated voltage reference and a

comparator circuit that monitors the V

level. The device is fully accessible and data can be written and read when

is greater than V

. However, when V

falls below V

, the internal clock registers are blocked from any

access. If V

is less than V

BAT

, the device power is switched from V

to V

BAT

when V

drops below V

. If V

greater than V

BAT

, the device power is switched from V

to V

BAT

when V

drops below V

BAT

. The registers are

maintained from the V

BAT

source until V

is returned to nominal levels (Table 1). After V

returns above V

, read

and write access is allowed after t

REC

(Figure 1). On the first application of power to the device the time and date

registers are reset to 01/01/00 01 00:00:00 (DD/MM/YY DOW HH:MM:SS). The CH bit in the seconds register will be set

to a 0.

Table 1. Power Control

SUPPLY

CONDITION

READ/WRITE

ACCESS

POWERED

< V

, V

< V

BAT

< V

, V

> V

BAT

> V

, V

< V

BAT

Yes

> V

, V

> V

BAT

Yes

OSCILLATOR CIRCUIT

The DS1338 uses an external 32.768kHz crystal. The oscillator circuit does not require any external resistors or

capacitors to operate. Table 2 specifies several crystal parameters for the external crystal. Figure 3 shows a

functional schematic of the oscillator circuit. The startup time is usually less than 1 second when using a crystal

with the specified characteristics.

Table 2. Crystal Specifications

PARAMETER SYMBOL MIN TYP MAX UNITS

Nominal Frequency f

32.768 kHz

Series Resistance ESR 50

kΩ

Load Capacitance C

12.5 pF

*The crystal, traces, and crystal input pins should be isolated from RF generating signals. Refer to

Application Note 58: Crystal Considerations for Dallas Real-Time Clocks for additional specifications.

DS1338 I

C RTC with 56-Byte NV RAM

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CLOCK ACCURACY

The accuracy of the clock is dependent upon the accuracy of the crystal and the accuracy of the match between

the capacitive load of the oscillator circuit and the capacitive load for which the crystal was trimmed. Crystal

frequency drift caused by temperature shifts creates additional error. External circuit noise coupled into the

oscillator circuit can result in the clock running fast. Figure 4 shows a typical PC board layout for isolating the

crystal and oscillator from noise. Refer to Application Note 58: Crystal Considerations with Dallas Real-Time Clocks

for detailed information.

DS1338C ONLY

The DS1338C integrates a standard 32,768Hz crystal in the package. Typical accuracy at nominal V

and +25°C

is approximately 10ppm. Refer to Application Note 58 for information about crystal accuracy vs. temperature.

Figure 4. Typical PC Board Layout for Crystal

RTC AND RAM ADDRESS MAP

Table 3 shows the address map for the RTC and RAM registers. The RTC registers and control register are located

in address locations 00h to 07h. The RAM registers are located in address locations 08h to 3Fh. During a multibyte

access, when the register pointer reaches 3Fh (the end of RAM space) it wraps around to location 00h (the

beginning of the clock space). On an I

C START, STOP, or register pointer incrementing to location 00h, the

current time and date is transferred to a second set of registers. The time and date in the secondary registers are

read in a multibyte data transfer, while the clock continues to run. This eliminates the need to re-read the registers

in case of an update of the main registers during a read.

CLOCK AND CALENDAR

The time and calendar information is obtained by reading the appropriate register bytes. See Figure 6 for the RTC

registers. The time and calendar are set or initialized by writing the appropriate register bytes. The contents of the

time and calendar registers are in the BCD format. Bit 7 of Register 0 is the clock halt (CH) bit. When this bit is set

to 1, the oscillator is disabled. When cleared to 0, the oscillator is enabled. The clock can be halted whenever the

timekeeping functions are not required, which minimizes V

BAT

current (I

BATDAT

) when VCC is not applied.

The day-of-week register increments at midnight. Values that correspond to the day of week are user-defined but

must be sequential (i.e., if 1 equals Sunday, then 2 equals Monday, and so on). Illogical time and date entries

result in undefined operation.

When reading or writing the time and date registers, secondary (user) buffers are used to prevent errors when the

internal registers update. When reading the time and date registers, the user buffers are synchronized to the

internal registers on any start or stop and when the register pointer rolls over to zero. The countdown chain is reset

LOCAL GROUND PLANE (LAYER 2)

CRYSTAL

GND

NOTE: AVOID ROUTING SIGNALS IN THE CROSSHATCHED

AREA (UPPER LEFT-HAND QUADRANT) OF THE PACKAGE

UNLESS THERE IS A GROUND PLANE BETWEEN THE SIGNAL

LINE AND THE PACKAGE.

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DS1338U-3

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DS1338U-3

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