AT29LV256
3
will start. A6 to A14 specify the sector address. The sector
address must be valid during each high to low transition of
WE
(or CE). A0 to A5 specify the byte address within the
sector. The bytes may be loaded in any order; sequential
loading is not required. Once a programming operation has
been initiated, and for the duration of t
WC
, a read operation
will effectively be a polling operation.
HARDWARE DATA PROTECTION:
Hardware features
protect against inadvertent programs to the AT29LV256 in
the following ways: (a) V
CC
sense—if V
CC
is below 1.8V
(typical), the program function is inhibited; (b) V
CC
power on
delay—once V
CC
has reached the V
CC
sense level, the
device will automatically time out 10 ms (typical) before
programming; (c) Program inhibit— olding any one of OE
low, CE high or WE high inhibits program cycles; and
(d) Noise filter—pulses of less than 15 ns (typical) on the
WE
or CE inputs will not initiate a program cycle.
INPUT LEVELS:
While operating with a 3.3V ±10% power
supply, the address inputs and control inputs (OE
, CE and
WE
) may be driven from 0 to 5.5V without adversely affect-
ing the operation of the device. The I/O lines can only be
driven from 0 to 3.6 volts.
PRODUCT IDENTIFICATION:
The product identification
mode identifies the device and manufacturer as Atmel. It
may be accessed by hardware or software operation. The
hardware operation mode can be used by an external pro-
grammer to identify the correct programming algorithm for
the Atmel product. In addition, users may wish to use the
software product identification mode to identify the part (i.e.
using the device code), and have the system software use
the appropriate sector size for program operations. In this
manner, the user can have a common board design for
256K to 4-megabit densities and, with each density’s sector
size in a memory map, have the system software apply the
appropriate sector size.
For details, see Operating Modes (for hardware operation)
or Software Product Identification. The manufacturer and
device code is the same for both modes.
DATA
POLLING:
The AT29LV256 features DATA
polling
to indicate the end of a program cycle. During a program
cycle an attempted read of the last byte loaded will result in
the complement of the loaded data on I/O7. Once the pro-
gram cycle has been completed, true data is valid on all
outputs and the next cycle may begin. DATA
polling may
begin at any time during the program cycle.
TOGGLE BIT:
In addition to DATA
polling the
AT29LV256 provides another method for determining the
end of a program or erase cycle. During a program or erase
operation, successive attempts to read data from the
device will result in I/O6 toggling between one and zero.
Once the program cycle has completed, I/O6 will stop tog-
gling and valid data will be read. Examining the toggle bit
may begin at any time during a program cycle.
OPTIONAL CHIP ERASE MODE:
The entire device can
be erased by using a 6-byte software code. Please see
Software Chip Erase application note for details.
Absolute Maximum Ratings*
Temperature Under Bias................................ -55
°
C to +125
°
C
*NOTICE: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability.
Storage Temperature..................................... -65
°
C to +150
°
C
All Input Voltages (including NC Pins)
with Respect to Ground...................................-0.6V to +6.25V
All Output Voltages
with Respect to Ground.............................-0.6V to V
CC
+ 0.6V
Voltage on A9 (including NC Pins)
with Respect to Ground...................................-0.6V to +13.5V
