16
LTC3776
3776fa
Operating Frequency and Synchronization
The choice of operating frequency, f
OSC
, is a trade-off
between efficiency and component size. Low frequency
operation improves efficiency by reducing MOSFET switch-
ing losses, both gate charge loss and transition loss.
However, lower frequency operation requires more induc-
tance for a given amount of ripple current.
The internal oscillator for each of the LTC3776’s control-
lers runs at a nominal 550kHz frequency when the PLLLPF
pin is left floating and the SYNC/SSEN pin is tied to GND.
Pulling the PLLLPF to V
IN
selects 750kHz operation;
pulling the PLLLPF to GND selects 300kHz operation.
Alternatively, the LTC3776 will phase-lock to a clock signal
applied to the SYNC/SSEN pin with a frequency between
250kHz and 850kHz (see Phase-Locked Loop and Fre-
quency Synchronization).
When spread spectrum operation is enabled (SYNC/
SSEN = V
IN
), the frequency of the LTC3776 is randomly
varied over the range of frequencies between 450kHz and
580kHz. In this case, a capacitor (1nF to 4.7nF) should be
connected between the FREQ pin and SGND to smooth
out the changes in frequency. This not only provides a
smoother frequency spectrum but also ensures that the
switching regulator remains stable by preventing abrupt
changes in frequency. A value of 2200pF is suitable in
most applications.
Inductor Value Calculation
Given the desired input and output voltages, the inductor
value and operating frequency f
OSC
directly determine the
inductor’s peak-to-peak ripple current:
I
V
V
VV
fL
RIPPLE
OUT
IN
IN OUT
OSC
=
Lower ripple current reduces core losses in the inductor,
ESR losses in the output capacitors, and output voltage
ripple. Thus, highest efficiency operation is obtained at
low frequency with a small ripple current. Achieving this,
however, requires a large inductor.
A reasonable starting point is to choose a ripple current
that is about 40% of I
OUT(MAX)
. Note that the largest ripple
current occurs at the highest input voltage. To guarantee
that ripple current does not exceed a specified maximum,
the inductor should be chosen according to:
L
VV
fI
V
V
IN OUT
OSC RIPPLE
OUT
IN
Inductor Core Selection
Once the inductance value is determined, the type of
inductor must be selected. Actual core loss is independent
of core size for a fixed inductor value, but it is very
dependent on inductance selected. As inductance in-
creases, core losses go down. Unfortunately, increased
inductance requires more turns of wire and therefore
copper losses will increase.
Ferrite designs have very low core loss and are preferred
at high switching frequencies, so design goals can
concentrate on copper loss and preventing saturation.
Ferrite core material saturates “hard,” which means that
inductance collapses abruptly when the peak design cur-
rent is exceeded. This results in an abrupt increase in
inductor ripple current and consequent output voltage
ripple. Do not allow the core to saturate!
Different core materials and shapes will change the size/
current and price/current relationship of an inductor.
Toroid or shielded pot cores in ferrite or permalloy
materials are small and don’t radiate much energy, but
generally cost more than powdered iron core inductors
with similar characteristics. The choice of which style
inductor to use mainly depends on the price vs size
requirements and any radiated field/EMI requirements.
New designs for surface mount inductors are available
from Coiltronics, Coilcraft, Toko and Sumida.
Schottky Diode Selection (Optional)
The Schottky diodes D1 and D2 in Figure 16 conduct
current during the dead time between the conduction of
the power MOSFETs . This prevents the body diode of the
bottom N-channel MOSFET from turning on and storing
charge during the dead time, which could cost as much as
1% in efficiency. A 1A Schottky diode is generally a good
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17
LTC3776
3776fa
size for most LTC3776 applications, since it conducts a
relatively small average current. Larger diodes result in
additional transition losses due to their larger junction
capacitance. This diode may be omitted if the efficiency
loss can be tolerated.
C
IN
and C
OUT
Selection
The selection of C
IN
is simplified by the 2-phase architec-
ture and its impact on the worst-case RMS current drawn
through the input network (battery/fuse/capacitor). It can
be shown that the worst-case capacitor RMS current
occurs when only one controller is operating. The control-
ler with the highest (V
OUT
)(I
OUT
) product needs to be used
in the formula below to determine the maximum RMS
capacitor current requirement. Increasing the output cur-
rent drawn from the other controller will actually decrease
the input RMS ripple current from its maximum value. The
out-of-phase technique typically reduces the input
capacitor’s RMS ripple current by a factor of 30% to 70%
when compared to a single phase power supply solution.
In continuous mode, the source current of the P-channel
MOSFET is a square wave of duty cycle (V
OUT
)/(V
IN
). To
prevent large voltage transients, a low ESR capacitor sized
for the maximum RMS current of one channel must be
used. The maximum RMS capacitor current is given by:
C
I
V
VVV
IN
MAX
IN
OUT IN OUT
Required I
RMS
()( )
[]
/12
This formula has a maximum at V
IN
= 2V
OUT
, where I
RMS
= I
OUT
/2. This simple worst-case condition is commonly
used for design because even significant deviations do not
offer much relief. Note that capacitor manufacturers’
ripple current ratings are often based on only 2000 hours
of life. This makes it advisable to further derate the
capacitor, or to choose a capacitor rated at a higher
temperature than required. Several capacitors may be
paralleled to meet size or height requirements in the
design. Due to the high operating frequency of the LTC3776,
ceramic capacitors can also be used for C
IN
. Always
consult the manufacturer if there is any question.
The benefit of the LTC3776 2-phase operation can be cal-
culated by using the equation above for the higher power
controller and then calculating the loss that would have
resulted if both controller channels switched on at the
same time. The total RMS power lost is lower when both
controllers are operating due to the reduced overlap of
current pulses required through the input capacitor’s ESR.
This is why the input capacitor’s requirement calculated
above for the worst-case controller is adequate for the
dual controller design. Also, the input protection fuse re-
sistance, battery resistance, and PC board trace resistance
losses are also reduced due to the reduced peak currents
in a 2-phase system. The overall benefit of a multiphase
design will only be fully realized when the source imped-
ance of the power supply/battery is included in the effi-
ciency testing. The sources of the P-channel MOSFETs
should be placed within 1cm of each other and share a
common C
IN
(s). Separating the sources and C
IN
may pro-
duce undesirable voltage and current resonances at V
IN
.
A small (0.1μF to 1μF) bypass capacitor between the chip
V
IN
pin and ground, placed close to the LTC3776, is also
suggested. A 10Ω resistor placed between C
IN
(C1) and
the V
IN
pin provides further isolation between the two
channels.
The selection of C
OUT
is driven by the effective series
resistance (ESR). Typically, once the ESR requirement is
satisfied, the capacitance is adequate for filtering. The
output ripple (ΔV
OUT
) is approximated by:
Δ≈ +
V I ESR
fC
OUT RIPPLE
OUT
1
8
where f is the operating frequency, C
OUT
is the output
capacitance and I
RIPPLE
is the ripple current in the induc-
tor. The output ripple is highest at maximum input voltage
since I
RIPPLE
increases with input voltage.
Setting Output Voltage
The LTC3776’s channel 1 output voltage is set by an
external feedback resistor divider carefully placed across
the output, as shown in Figure 6. The regulated output
voltage is determined by:
VV
R
R
OUT
B
A
1
06 1=+
.•
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18
LTC3776
3776fa
During soft-start, the start-up of V
OUT1
is controlled by
slowly ramping the positive reference to the error amplifier
from 0V to 0.6V, allowing V
OUT1
to rise smoothly from 0V
to its final value. The default internal soft-start time is 1ms.
This can be increased by placing a capacitor between the
RUN/SS pin and SGND. In this case, the soft-start time will
be approximately:
tC
mV
A
SS SS1
600
07
=
μ
.
V
REF
Pin
The regulation of V
OUT2
is controlled by the voltage on the
V
REF
pin. Normally this pin is used in DDR memory
termination applications so that V
OUT2
tracks 1/2 V
OUT1
as
shown in Figure 8.
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3.3V OR 5V RUN/SS RUN/SS
C
SS
C
SS
D1
3776 F07
Figure 7. RUN/SS Pin Interfacing
Channel 2’s output voltage is set to 1/2 V
REF
by connecting
the V
FB2
pin to V
OUT2
. To improve the frequency response,
a feed-forward capacitor, C
FF
, may be used. Great care
should be taken to route the V
FB
line away from noise
sources, such as the inductor or the SW line.
LTC3776
V
FB2
V
FB1
V
OUT1
V
OUT2
R
B
C
FF
R
A
3776 F06
Figure 6. Setting Output Voltage
Run/Soft Start Function
The RUN/SS pin is a dual purpose pin that provides the
optional external soft-start function and a means to shut
down the LTC3776.
Pulling the RUN/SS pin below 0.65V puts the LTC3776 into
a low quiescent current shutdown mode (I
Q
= 9μA). If
RUN/SS has been pulled all the way to ground, there will
be a delay before the LTC3776 comes out of shutdown and
is given by:
tV
C
A
sFC
DELAY
SS
SS
=
μ
= μ065
07
093.•
.
./
This pin can be driven directly from logic as shown in
Figure 7. Diode D1 in Figure 7 reduces the start delay but
allows C
SS
to ramp up slowly providing the soft-start
function. This diode (and capacitor) can be deleted if the
external soft-start is not needed.
LTC3776
V
FB2
V
OUT2
V
OUT1
V
FB1
V
REF
3776 F08
R1B
R1A
Figure 8. Using the V
REF
Pin (V
OUT2
is Regulated to 1/2 V
REF
= 1/2V
OUT1
)
Phase-Locked Loop and Frequency Synchronization
The LTC3776 has a phase-locked loop (PLL) comprised
of an internal voltage-controlled oscillator (VCO) and a
phase detector. This allows the turn-on of the external
P-channel MOSFET of controller 1 to be locked to the
rising edge of an external clock signal applied to the
SYNC/SSEN pin. The turn-on of controller 2’s external
P-channel MOSFET is thus 180 degrees out of phase with
the external clock. The phase detector is an edge sensitive
digital type that provides zero degrees phase shift
between the external and internal oscillators. This type of
phase detector does not exhibit false lock to harmonics of
the external clock.
The output of the phase detector is a pair of complemen-
tary current sources that charge or discharge the external
filter network connected to the PLLLPF pin. The relation-
ship between the voltage on the PLLLPF pin and operating

LTC3776EGN#PBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators 2x 2-Phase, No RSENSE Sync Cntr for DDR/
Lifecycle:
New from this manufacturer.
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