Data Sheet ADuM1410/ADuM1411/ADuM1412
APPLICATIONS INFORMATION
PC BOARD LAYOUT
The ADuM1410/ADuM1411/ADuM1412 digital isolators
require no external interface circuitry for the logic interfaces.
Power supply bypassing is strongly recommended at the input
and output supply pins (see Figure 16). Bypass capacitors are
most conveniently connected between Pin 1 and Pin 2 for V
DD1
,
and between Pin 15 and Pin 16 for V
DD2
. The capacitor value
should be between 0.01 µF and 0.1 µF. The total lead length
between both ends of the capacitor and the input power supply
pin should not exceed 20 mm. Bypassing between Pin 1 and Pin 8
and between Pin 9 and Pin 16 should also be considered unless
both ground pins on each package are connected together close to
the package.
V
DD1
GND
1
V
IA
V
IB
V
IC
V
ID
DISABLE
GND
1
V
DD2
GND
2
V
OA
V
OB
V
OC
V
OD
CTRL
2
GND
2
06580-016
ADuM1410
Figure 16. Recommended Printed Circuit Board Layout
In applications involving high common-mode transients, it is
important to minimize board coupling across the isolation barrier.
Furthermore, users should design the board layout so that any
coupling that does occur equally affects all pins on a given
component side. Failure to ensure this can cause voltage
differentials between pins exceeding the absolute maximum
ratings of the device, thereby leading to latch-up or permanent
damage. See the AN-1109 Application Note for board layout
guidelines.
PROPAGATION DELAY-RELATED PARAMETERS
Propagation delay is a parameter that describes the time it takes
a logic signal to propagate through a component. The input-to-
output propagation delay time for a high-to-low transition may
differ from the propagation delay time of a low-to-high transition.
INPUT (V
Ix
)
OUTPUT (V
Ox
)
t
PLH
t
PHL
50%
50%
06580-017
Figure 17. Propagation Delay Parameters
Pulse width distortion is the maximum difference between these
two propagation delay values and an indication of how accurately
the timing of the input signal is preserved.
Channel-to-channel matching refers to the maximum amount
the propagation delay differs between channels within a single
ADuM1410/ADuM1411/ADuM1412 component.
Propagation delay skew refers to the maximum amount the
propagation delay differs between multiple ADuM1410/
ADuM1411/ADuM1412 components operating under the same
conditions.
DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY
Positive and negative logic transitions at the isolator input
cause narrow (~1 ns) pulses to be sent to the decoder using the
transformer. The decoder is bistable and is, therefore, either set
or reset by the pulses, indicating input logic transitions. In the
absence of logic transitions at the input for more than ~1 µs, a
periodic set of refresh pulses indicative of the correct input state
is sent to ensure dc correctness at the output. If the decoder
receives no internal pulses of more than approximately 5 µs, the
input side is assumed to be unpowered or nonfunctional, in
which case the isolator output is forced to a default state (see
Table 14) by the watchdog timer circuit.
The magnetic field immunity of the ADuM1410/ADuM1411/
ADuM1412 is determined by the changing magnetic field, which
induces a voltage in the transformer’s receiving coil large enough
to either falsely set or reset the decoder. The following analysis
defines the conditions under which this can occur. The 3 V
operating condition of the ADuM1410/ADuM1411/ADuM1412
is examined because it represents the most susceptible mode of
operation.
The pulses at the transformer output have an amplitude greater
than 1.0 V. The decoder has a sensing threshold at about 0.5 V, thus
establishing a 0.5 V margin in which induced voltages can be
tolerated. The voltage induced across the receiving coil is given by
V = (−dβ/dt) ∑ π r
n
2
; n = 1, 2, … , N
where:
β is magnetic flux density (gauss).
r
n
is the radius of the n
th
turn in the receiving coil (cm).
N is the number of turns in the receiving coil.
Given the geometry of the receiving coil in the ADuM1410/
ADuM1411/ADuM1412 and an imposed requirement that the
induced voltage be, at most, 50% of the 0.5 V margin at the
decoder, a maximum allowable magnetic field at a given frequency
can be calculated. The result is shown in Figure 18.
MAGNETIC FIELD FREQUENCY (Hz)
100
MAXIMUM ALLOWABLE MAGNETIC FLUX
DENSITY (kgauss)
0.001
1M
10
0.01
1k 10k 10M
0.1
1
100M100k
06580-018
Figure 18. Maximum Allowable External Magnetic Flux Density
Rev. M | Page 19 of 22
