ISL6228HRTZ-T Datasheet ISL6228IRTZ, ISL6228HRTZ, ISL6228HRTZ-T | P10-P12

FN9095.2

May 7, 2008

The ISL6228 monitors the OCSET pin and the VO pin

voltages. Once the OCSET pin voltage is higher than the VO

pin voltage for more than 10µs, the ISL6228 declares an OCP

fault. The value of R

OCSET

is then written as Equation 6:

Where:

-R

OCSET

(Ω) is the resistor used to program the

overcurrent setpoint

-I

is the output current threshold that will activate the

OCP circuit

- DCR is the inductor DC resistance

For example, if I

is 20A and DCR is 4.5mΩ, the choice of

OCSET

is R

OCSET

= 20A x 4.5mΩ/10µA = 9kΩ.

Resistor R

OCSET

and capacitor C

SEN

form an R-C network

to sense the inductor current. To sense the inductor current

correctly not only in DC operation, but also during dynamic

operation, the R-C network time constant R

OCSET

SEN

needs to match the inductor time constant L/DCR. The value

of C

SEN

is then written as Equation 7:

For example, if L is 1.5µH, DCR is 4.5mΩ, and R

OCSET

9kΩ, the choice of C

SEN

= 1.5µH/(9kΩ x 4.5mΩ) = 0.037µF.

Upon converter startup, capacitor C

SEN

initial voltage is 0V.

To prevent false OCP, a 10µA current source flows out of the

VO pin during start up, generating a voltage drop on resistor

, which has the same resistance as R

OCSET

. When

PGOOD pin goes high, the VO pin current source will

terminate.

When an OCP fault is declared, the PGOOD pin will pull

down to 30Ω

and latch off the converter. The fault will remain

latched until the EN pin has been pulled below the falling EN

threshold voltage V

ENTHF

or if V

has decayed below the

falling POR threshold voltage

VCC_THF

Overvoltage Protection

The OVP fault detection circuit triggers after the FB pin voltage

is above the rising overvoltage threshold V

OVR

for more than

2µs. The FB pin voltage is 0.6V in normal operation. The rising

overvoltage threshold V

OVR

is typically 116%. That means if

the FB pin voltage is above 116% x 0.6V = 0.696V, for more

than 2µs, an OVP fault is declared.

When an OVP fault is declared, the PGOOD pin will pull

down to 60Ω

and latch-off the converter. The OVP fault will

remain latched until the EN pin has been pulled below the

falling EN threshold voltage V

ENTHF

or if V

has decayed

below the falling POR threshold voltage

VCC_THF

Although the converter has latched-off in response to an

OVP fault, the LGATE gate-driver output will retain the ability

to toggle the low-side MOSFET on and off, in response to

the output voltage transversing the V

OVR

and V

OVF

thresholds. The LGATE gate-driver will turn on the low-side

MOSFET to discharge the output voltage, protecting the

load. The LGATE gate-driver will turn off the low-side

MOSFET once the FB pin voltage is lower than the falling

overvoltage threshold V

OVF

for more than 2µs. The falling

overvoltage threshold V

OVF

is typically 106%. That means if

the FB pin voltage falls below 106% x 0.6V = 0.636V, for

more than 2µs, the LGATE gate-driver will turn off the low-

side MOSFET. If the output voltage rises again, the LGATE

driver will again turn on the low-side MOSFET when the FB

pin voltage is above the rising overvoltage threshold V

OVR

for more than 2µs. By doing so, the ISL6228 protects the

load when there is a consistent overvoltage condition.

Undervoltage Protection

The UVP fault detection circuit triggers after the FB pin

voltage is below the undervoltage threshold V

for more

than 2µs. The FB pin voltage is 0.6V in normal operation.

The undervoltage threshold V

is typically 86%. That

means if the FB pin voltage is below 86% x 0.6V = 0.516V,

for more than 2µs, an UVP fault is declared, and the

PGOOD pin will pull down to 95Ω

and latch-off the converter.

The fault will remain latched until the EN pin has been pulled

below the falling EN threshold voltage V

ENTHF

or if V

has

decayed below the falling POR threshold voltage

VCC_THF

Programming the Output Voltage

When the converter is in regulation there will be 0.6V from

the FB pin to the GND pin. Connect a two-resistor voltage

divider across the VO pin and the GND pin with the output

node connected to the FB pin. Scale the voltage-divider

network such that the FB pin is 0.6V with respect to the GND

pin when the converter is regulating at the desired output

voltage. The output voltage can be programmed from 0.6V

to 5V.

Programming the output voltage is written as Equation 8:

Where:

-V

is the desired output voltage of the converter

- The voltage to which the converter regulates the FB pin

is the V

REF

-R

TOP

is the voltage-programming resistor that connects

from the FB pin to the converter output. In addition to

setting the output voltage, this resistor is part of the loop

compensation network

-R

BOTTOM

is the voltage-programming resistor that

connects from the FB pin to the GND pin

Choose R

TOP

value first, and calculate R

BOTTOM

according

to Equation 9:

(EQ. 6)

OCSET

DCR•

10μA

---------------------------

(EQ. 7)

SEN

OCSET

DCR•

-----------------------------------------

REF

BOTTOM

TOP

BOTTOM

---------------------------------------------------

•=

(EQ. 8)

BOTTOM

REF

R•

TOP

REF

–

-----------------------------------

(EQ. 9)

ISL6228

FN9095.2

May 7, 2008

Programming the PWM Switching Frequency

The ISL6228 does not use a clock signal to produce PWMs.

The PWM switching frequency f

is programmed by the

resistor R

FSET

that is connected from the FSET pin to the

GND pin. The approximate PWM switching frequency is

written as Equation 10:

Estimating the value of R

FSET

is written as Equation 11:

Where:

-f

is the PWM switching frequency

-R

FSET

is the f

programming resistor

- K = 1.5 x 10

-10

It is recommended that whenever the control loop

compensation network is modified, f

should be checked

for the correct frequency and if necessary, adjust R

FSET

Compensation Design

Figure 6 shows the recommended Type-II compensation

circuit. The FB pin is the inverting input of the error amplifier.

The COMP signal, the output of the error amplifier, is inside the

chip and unavailable to users. C

INT

is a 100pF capacitor

integrated inside the IC, connecting across the FB pin and the

COMP signal. R

TOP

, R

, C

and C

INT

form the Type-II

compensator. The frequency domain transfer function is given

by Equation 12:

The LC output filter has a double pole at its resonant frequency

that causes rapid phase change. The R

modulator used in the

ISL6228 makes the LC output filter resemble a first order

system in which the closed loop stability can be achieved with

the recommended Type-II compensation network. Intersil

provides a PC-based tool (example page is shown later) that

can be used to calculate compensation network component

values and help simulate the loop frequency response.

General Application Design Guide

This design guide is intended to provide a high-level

explanation of the steps necessary to design a single-phase

power converter. It is assumed that the reader is familiar with

many of the basic skills and techniques referenced in the

following section. In addition to this guide, Intersil provides

complete reference designs that include schematics, bills of

materials, and example board layouts.

Selecting the LC Output Filter

The duty cycle of an ideal buck converter is a function of the

input and the output voltage. This relationship is written as

Equation 13:

The output inductor peak-to-peak ripple current is written as

Equation 14:

A typical step-down DC/DC converter will have an I

P-P

20% to 40% of the maximum DC output load current. The

value of I

is selected based upon several criteria such as

MOSFET switching loss, inductor core loss, and the resistive

loss of the inductor winding. The DC copper loss of the

inductor can be estimated by Equation 15:

Where I

LOAD

is the converter output DC current.

The copper loss can be significant so attention has to be

given to the DCR selection. Another factor to consider when

choosing the inductor is its saturation characteristics at

elevated temperature. A saturated inductor could cause

destruction of circuit components, as well as nuisance OCP

faults.

A DC/DC buck regulator must have output capacitance C

into which ripple current I

P-P

can flow. Current I

develops

a corresponding ripple voltage V

P-P

across C

which is the

sum of the voltage drop across the capacitor ESR and of the

voltage change stemming from charge moved in and out of

the capacitor. These two voltages are written as

Equation 16:

and Equation 17:

If the output of the converter has to support a load with high

pulsating current, several capacitors will need to be paralleled

to reduce the total ESR until the required V

P-P

is achieved.

The inductance of the capacitor can cause a brief voltage dip

if the load transient has an extremely high slew rate. Low

inductance capacitors should be considered. A capacitor

FSET

⋅

---------------------------

(EQ. 10)

FSET

•

------------------

(EQ. 11)

(EQ. 12)

COMP

s()

1sR

TOP

+()C•

•+

TOP

INT

1sR

C•

•+()•••

-------------------------------------------------------------------------------------------

ISL6228

BOTTOM

INT

= 100pF

REF

FIGURE 6. COMPENSATION REFERENCE CIRCUIT

TOP

COMP

---------

(EQ. 13)

(EQ. 14)

1D–()•

L•

------------------------------

(EQ. 15)

COPPER

LOAD

DCR•=

ΔV

ESR

P-P

E• SR=

(EQ. 16)

ΔV

P-P

f•

•

-----------------------------

(EQ. 17)

ISL6228

FN9095.2

May 7, 2008

dissipates heat as a function of RMS current and frequency.

Be sure that I

P-P

is shared by a sufficient quantity of paralleled

capacitors so that they operate below the maximum rated

RMS current at f

. Take into account that the rated value of

a capacitor can fade as much as 50% as the DC voltage

across it increases.

Selection of the Input Capacitor

The important parameters for the bulk input capacitance are

the voltage rating and the RMS current rating. For reliable

operation, select bulk capacitors with voltage and current

ratings above the maximum input voltage and capable of

supplying the RMS current required by the switching circuit.

Their voltage rating should be at least 1.25 times greater

than the maximum input voltage, while a voltage rating of 1.5

times is a preferred rating. Figure 7 is a graph of the input

RMS ripple current, normalized relative to output load current,

as a function of duty cycle that is adjusted for converter

efficiency. The ripple current calculation is written as

Equation 18:

Where:

-I

MAX

is the maximum continuous I

LOAD

of the converter

- x is a multiplier (0 to 1) corresponding to the inductor

peak-to-peak ripple amplitude expressed as a

percentage of I

MAX

(0% to 100%)

- D is the duty cycle that is adjusted to take into account

the efficiency of the converter which is written as:

In addition to the bulk capacitance, some low ESL ceramic

capacitance is recommended to decouple between the drain

of the high-side MOSFET and the source of the low-side

MOSFET.

MOSFET Selection and Considerations

Typically, a MOSFET cannot tolerate even brief excursions

beyond their maximum drain to source voltage rating. The

MOSFETs used in the power stage of the converter should

have a maximum V

rating that exceeds the sum of the

upper voltage tolerance of the input power source and the

voltage spike that occurs when the MOSFET switches off.

There are several power MOSFETs readily available that are

optimized for DC/DC converter applications. The preferred

high-side MOSFET emphasizes low gate charge so that the

device spends the least amount of time dissipating power in

the linear region. Unlike the low-side MOSFET which has the

drain-source voltage clamped by its body diode during turn

off, the high-side MOSFET turns off with V

-V

OUT

, plus the

spike, across it. The preferred low-side MOSFET

emphasizes low r

DS(ON)

when fully saturated to minimize

conduction loss.

For the low-side (LS) MOSFET, the power loss can be

assumed to be conductive only and is written as Equation 20:

For the high-side (HS) MOSFET, the its conduction loss is

written as Equation 21:

For the high-side MOSFET, the switching loss is written as

Equation 22:

Where:

-I

VALLEY

is the difference of the DC component of the

inductor current minus 1/2 of the inductor ripple current

-I

PEAK

is the sum of the DC component of the inductor

current plus 1/2 of the inductor ripple current

-t

is the time required to drive the device into

saturation

-t

OFF

is the time required to drive the device into cut-off

Selecting The Bootstrap Capacitor

The selection of the bootstrap capacitor is written as

Equation 23:

Where:

-Q

is the total gate charge required to turn on the

high-side MOSFET

- ΔV

BOOT

, is the maximum allowed voltage decay across

the boot capacitor each time the high-side MOSFET is

switched on

(EQ. 18)

IN_RMS NORMALIZED,

MAX

–()⋅()xI

MAX

------

⋅⋅

⎝⎠

⎛⎞

MAX

-----------------------------------------------------------------------------------------------------

EFF⋅

--------------------------

(EQ. 19)

FIGURE 7. NORMALIZED RMS INPUT CURRENT

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

0.05

0.10

0.15

0.20

0.25

0.30

0.35

0.40

0.45

0.50

0.55

0.60

NORMALIZED INPUT RMS RIPPLE CURRENT

DUTY CYCLE

x = 1

x = 0.75

x = 0.50

x = 0.25

x = 0

(EQ. 20)

CON_LS

LOAD

r⋅

DS ON()_LS

1D–()•≈

(EQ. 21)

CON_HS

LOAD

r•

DS ON()_HS

D•=

(EQ. 22)

SW_HS

VALLEY

f•

••

-----------------------------------------------------------------

PEAK

OFF

f•

••

-------------------------------------------------------------

BOOT

ΔV

BOOT

------------------------

(EQ. 23)

ISL6228

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P16

ISL6228HRTZ-T

Mfr. #:

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Manufacturer:

Renesas / Intersil

Description:

Switching Controllers ISL6228 NOTEBOOK DL CNTRLR 4X4 TQFN T

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