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NLSF3T125MNR2G

P1-P3P4-P6
© Semiconductor Components Industries, LLC, 2011
June, 2011 − Rev. 5
1 Publication Order Number:
NLSF3T125/D
NLSF3T125
Quad Bus Buffer
with 3−State Control Inputs
The NLSF3T125 is a high speed CMOS quad bus buffer fabricated
with silicon gate CMOS technology. It achieves high speed operation
similar to equivalent Bipolar Schottky TTL while maintaining CMOS
low power dissipation.
The NLSF3T125 requires the 3−state control input (OE
) to be set
High to place the output into the high impedance state.
The T125 inputs are compatible with TTL levels. This device can be
used as a level converter for interfacing 3.3 V to 5.0 V, because it has
full 5.0 V CMOS level output swings.
The NLSF3T125 input structures provide protection when voltages
between 0 V and 5.5 V are applied, regardless of the supply voltage.
The output structures also provide protection when V
CC
= 0 V. These
input and output structures help prevent device destruction caused by
supply voltage − input/output voltage mismatch, battery backup, hot
insertion, etc.
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output. The
inputs tolerate voltages up to 7.0 V, allowing the interface of 5.0 V
systems to 3.0 V systems.
Features
• High Speed: t
PD
= 3.8 ns (Typ) at V
CC
= 5.0 V
• Low Power Dissipation: I
CC
= 4.0 mA (Max) at T
A
= 25°C
• TTL−Compatible Inputs: V
IL
= 0.8 V; V
IH
= 2.0 V
• Power Down Protection Provided on Inputs
• Balanced Propagation Delays
• Designed for 2.0 V to 5.5 V Operating Range
• Low Noise: V
OLP
= 0.8 V (Max)
• Pin and Function Compatible with Other Standard Logic Families
• Latchup Performance Exceeds 300 mA
• ESD Performance: Human Body Model; > 2000 V,
Machine Model; > 200 V
• Chip Complexity: 72 FETs or 18 Equivalent Gates
• These Devices are Pb−Free and are RoHS Compliant
NLSF3T125
Inputs Output
FUNCTION TABLE
YAOE
H
L
X
L
L
H
H
L
Z
MARKING DIAGRAM
QFN−16
CASE 485G
http://onsemi.com
NLSF3T125 = Specific Device Code
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
NLSF3
T125
ALYWG
G
(Note: Microdot may be in either location)
1
ORDERING INFORMATION
Device
QFN−16
(Pb−Free)
Shipping
†
3000/Tape & Reel
NLSF3T125MNR2G
Package
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
NLSF3T125
http://onsemi.com
2
Figure 1. Logic Diagram
Active−Low Output Enables
Y1
Y2
Y4
1
5
7
10
13
12
8
9
4
3
15
16
A1
OE1
A2
OE2
A3
OE3
A4
OE4
Y3
Figure 2. QFN − 16 Pinout (Top View)
Y2 GND Y3 A3
A1 OE1V
CC
OE4
A4
Y4
Y1
NC
OE
2
A2
NC
OE
3
Exposed Pad (EP)
1
3
4
5678
9
10
11
12
13141516
2
MAXIMUM RATINGS
Symbol Parameter Value Units
V
CC
DC Supply Voltage −0.5 to +7.0 V
V
in
DC Input Voltage –0.5 to +7.0 V
V
out
DC Output Voltage
Output in 3−State
High or Low State
–0.5 to +7.0
–0.5 to V
CC
+ 0.5
V
I
IK
Input Diode Current −20 mA
I
OK
Output Diode Current (V
OUT
< GND; V
OUT
> V
CC
) ±20 mA
I
out
DC Output Current, per Pin ±25 mA
I
CC
DC Supply Current, V
CC
and GND Pins ±75 mA
P
D
Power Dissipation in Still Air
QFN Packages
500
mW
T
stg
Storage Temperature –65 to +150 °C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress
ratings only. Functional operation above the Recommended Operating Conditions is not implied.
Extended exposure to stresses above the Recommended Operating Conditions may affect device
reliability.
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir-
cuit. For proper operation, V
in
and
V
out
should be constrained to the
range GND v (V
in
or V
out
) v V
CC
.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or V
CC
).
Unused outputs must be left open.
NLSF3T125
http://onsemi.com
3
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Units
V
CC
DC Supply Voltage 2.0 5.5 V
V
in
DC Input Voltage 0 5.5 V
V
out
DC Output Voltage
Output in 3−State
High or Low State
0
0
5.5
V
CC
V
T
A
Operating Temperature −40 +85 °C
t
r
, t
f
Input Rise and Fall Time
V
CC
= 5.0 V ±0.5 V 0 20
ns/V
DC ELECTRICAL CHARACTERISTICS
Parameter Test Conditions
V
CC
(V)
T
A
= 25°C T
A
3 85°C T
A
3 125°C
Units
Symbol Min Typ Max Min Max Min Max
V
IH
Minimum
High−Level
Input Voltage
2.3 V ± 0.3 V
3.3 V ± 0.3 V
5.0 V ± 0.5 V
0.5 V
CC
0.4 V
CC
0.44 V
CC
0.5 V
CC
0.4 V
CC
0.44 V
CC
0.5 V
CC
0.4 V
CC
0.44 V
CC
V
V
IL
Maximum
Low−Level
Input Voltage
2.3 V ± 0.3 V
3.3 V ± 0.3 V
5.0 V ± 0.5 V
0.3 V
CC
0.18 V
CC
0.18 V
CC
0.3 V
CC
0.18 V
CC
0.18 V
CC
0.3 V
CC
0.18 V
CC
0.18 V
CC
V
V
OH
Minimum
High−Level
Output Voltage
V
IN
= V
IH
or V
IL
V
OL
@ I
OL
, 50 mA
V
IN
= V
IH
or V
IL
I
OH
= −50 mA
2.0
3.0
4.5
1.9
2.9
4.4
2.0
3.0
4.5
1.9
2.9
4.4
1.9
2.9
4.4
V
V
IN
= V
IH
or V
IL
I
OH
= −2.0 mA
I
OH
= −4.0 mA
I
OH
= −8.0 mA
2.0
3.0
4.5
1.82
2.58
3.94
1.72
2.48
3.80
1.60
2.34
3.66
V
OL
Maximum
Low−Level
Output Voltage
V
IN
= V
IH
or V
IL
V
OL
@ I
OL
, 50 mA
V
IN
= V
IH
or V
IL
I
OL
= 50 mA
2.0
3.0
4.5
0.0
0.0
0.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
IN
= V
IH
or V
IL
I
OL
= 2.0 mA
I
OL
= 4.0 mA
I
OL
= 8.0 mA
2.0
3.0
4.5
0.36
0.36
0.36
0.44
0.44
0.44
0.52
0.52
0.52
I
IN
Maximum
Input Leakage
Current
V
IN
= 5.5 V or
GND
0
to
5.5
±0.1 ±1.0 ±1.0
mA
I
CC
Maximum
Quiescent
Supply Current
V
IN
= V
CC
or GND 5.5 2.0 20 40
mA
I
CCT
Quiescent
Supply
Current
Input: V
IN
= 3.4 V 5.5 1.35 1.50 1.65 mA
I
OZ
Maximum
3−State
Leakage
Current
V
IN
= V
IH
or V
IL
V
OUT
= V
CC
or GN
D
5.5 ±0.25 ±2.5 ±2.5
mA
I
OPD
Output
Leakage
Current
V
OUT
= 5.5 V 0.0 0.5 5.0 10
mA
P1-P3P4-P6

NLSF3T125MNR2G

Mfr. #:
Buy NLSF3T125MNR2G
Manufacturer:
ON Semiconductor
Description:
Buffers & Line Drivers 2-5.5V Quad Bus 4 State Control Inp.
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