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LT3435IFE#TRPBF

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LT3435
16
3435fa
Table 4. Catch Diode Selection Criteria
I
Q
at 125°C EFFICIENCY
LEAKAGE V
IN
=12V V
IN
=12V
V
OUT
= 3.3V V
F
AT 1A V
OUT
= 3.3 V
OUT
= 3.3V
DIODE 25°C 125°C25°C 125°CI
L
= 0A I
L
= 1A
IR 10BQ100 0.0µA59µA 0.72V 0.58V 125µA 74.7%
Diodes Inc. 0.1µA 242µA 0.48V 0.41V 215µA 81.7%
B260SMA
Diodes Inc. 0.2µA 440µA 0.45V 0.36V 270µA 82.4%
B360SMB
IR 1µA 1.81mA 0.42V 0.34V 821µA 82.7%
MBRS360TR
IR 30BQ100 1.7µA 2.64mA 0.40V 0.32V 1088µA 81.1%
If a no load condition can be anticipated, the supply current
can be further reduced by cycling the SHDN pin at a rate
higher than the natural no load burst frequency. Figure 6
shows Burst Mode operation with the SHDN pin. V
OUT
burst ripple is maintained while the average supply current
drops to 15µA. The PG pin will be active low during the
“on” portion of the SHDN waveform due to the C
T
capaci-
tor discharge when SHDN is taken low. See the Power
Good section for further information.
lack of a significant reverse recovery time. Schottky diodes
are generally available with reverse voltage ratings of 60V
and even 100V and are price competitive with other types.
The effect of reverse leakage and forward drop on effi-
ciency for various Schottky diodes is shown in Table 4. As
can be seen these are conflicting parameters and the user
must weigh the importance of each specification in choos-
ing the best diode for the application.
The use of so-called “ultrafast” recovery diodes is gener-
ally not recommended. When operating in continuous
mode, the reverse recovery time exhibited by “ultrafast”
diodes will result in a slingshot type effect. The power
internal switch will ramp up V
IN
current into the diode in an
attempt to get it to recover. Then, when the diode has
finally turned off, some tens of nanoseconds later, the V
SW
node voltage ramps up at an extremely high dV/dt, per-
haps 5V to even 10V/ns! With real world lead inductances
the V
SW
node can easily overshoot the V
IN
rail. This can
result in poor RFI behavior and, if the overshoot is severe
enough, damage the IC itself.
BOOST PIN
For most applications the boost components are a 0.33µF
capacitor and a MMSD914 diode. The anode is typically
connected to the regulated output voltage to generate a
voltage approximately V
OUT
above V
IN
to drive the output
stage (Figure 7a). However, the output stage discharges
the boost capacitor during the on time of the switch. The
output driver requires at least 2.5V of headroom through-
out this period to keep the switch fully saturated. If the
CATCH DIODE
The catch diode carries load current during the SW off
time. The average diode current is therefore dependent on
the switch duty cycle. At high input to output voltage ratios
the diode conducts most of the time. As the ratio ap-
proaches unity the diode conducts only a small fraction of
the time. The most stressful condition for the diode is
when the output is short circuited. Under this condition the
diode must safely handle I
PEAK
at maximum duty cycle.
To maximize high and low load current efficiency a fast
switching diode with low forward drop and low reverse
leakage should be used. Low reverse leakage is critical to
maximize low current efficiency since its value over tem-
perature can potentially exceed the magnitude of the
LT3435 supply current. Low forward drop is critical for
high current efficiency since the loss is proportional to
forward drop.
These requirements result in the use of a Schottky type
diode. DC switching losses are minimized due to its low
forward voltage drop and AC behavior is benign due to its
Figure 6. Burst Mode with Shutdown Pin
APPLICATIO S I FOR ATIO
WUUU
V
IN
= 12V 100ms/DIV 3435 F06
V
OUT
= 3.3V
I
Q
= 15µA
V
OUT
50mV/DIV
AC-COUPLED
I
SW
1A/DIV
V
SHDN
2V/DIV
LT3435
17
3435fa
A 0.33µF boost capacitor is recommended for most appli-
cations. Almost any type of film or ceramic capacitor is
suitable but the ESR should be <1Ω to ensure it can be fully
recharged during the off time of the switch. The capacitor
value is derived from worst-case conditions of 1700ns on
time, TBD boost current and 0.7V discharge ripple. The
boost capacitor value could be reduced under less de-
manding conditions but this will not improve circuit opera-
tion or efficiency. Under low input voltage and low load
conditions a higher value capacitor will reduce discharge
ripple and improve start-up operation.
SHUTDOWN FUNCTION AND UNDERVOLTAGE
LOCKOUT
The SHDN pin on the LT3435 controls the operation of the
IC. When the voltage on the SHDN pin is below the 1.2V
shutdown threshold the LT3435 is placed in a “zero”
supply current state. Driving the SHDN pin above the
shutdown threshold enables normal operation. The SHDN
pin has an internal sink current of 3µA.
In addition to the shutdown feature, the LT3435 has an
undervoltage lockout function. When the input voltage is
below 2.4V, switching will be disabled. The undervoltage
lockout threshold doesn’t have any hysteresis and is
mainly used to insure that all internal voltages are at the
correct level before switching is enabled. If an undervolt-
age lockout function with hysteresis is needed to limit
input current at low V
IN
to V
OUT
ratios refer to Figure 8 and
the following:
VR
V
R
V
R
IV
V
VR
R
UVLO
SHDN SHDN
SHDN SHDN
HYST
OUT
=++
⎛
⎝
⎜
⎞
⎠
⎟
+
=
()
1
32
1
3
R1 should be chosen to minimize quiescent current during
normal operation by the following equation:
R
VV
I
IN
SHDN MAX
1
2
15
=
()( )
–
.
()
Figure 7. BOOST Pin Configurations
output voltage is less than 3.3V it is recommended that an
alternate boost supply is used. The boost diode can be
connected to the input (Figure 7b) but care must be taken
to prevent the boost voltage (V
BOOST
= V
IN
• 2) from
exceeding the BOOST pin absolute maximum rating. The
additional voltage across the switch driver also increases
power loss and reduces efficiency. If available, an inde-
pendent supply can be used to generate the required
BOOST voltage (Figure 7c). Tying BOOST to V
IN
or an
independent supply may reduce efficiency but it will re-
duce the minimum V
IN
required to start-up with light
loads. If the generated BOOST voltage dissipates too
much power at maximum load, the BOOST voltage the
LT3435 sees can be reduced by placing a Zener diode in
series with the BOOST diode (Figure 7a option).
BOOST
LT3435
V
BOOST
– V
SW
= V
OUT
V
BOOST(MAX)
= V
IN
+ V
OUT
V
IN
V
OUT
OPTIONAL
(7a)
V
IN
SWGND
BOOST
LT3435
V
BOOST
– V
SW
= V
DC
V
BOOST(MAX)
= V
DC
+ V
IN
V
IN
V
DC
D
SS
3435 F07
V
OUT
(7c)
V
IN
SWGND
BOOST
LT3435
V
BOOST
– V
SW
= V
IN
V
BOOST(MAX)
= 2V
IN
V
IN
V
OUT
(7b)
V
IN
SWGND
APPLICATIO S I FOR ATIO
WUUU
LT3435
18
3435fa
Example:
R
A
M
R
M
M
A
M
k
1
12 2
155
13
3
513
1
65
1
13
649
408
=
µ
()
= Ω
=
Ω
()
= ΩΩ
Ω
µ
Ω
=
–
.
.
.
.
––
.
.
(Nearest 1% 6.49M )
R2 =
1.3
7 – 1.3
1.3M
(Nearest 1% 412k)
See the Typical Performance Characteristics section for
graphs of SHDN and V
IN
currents verses input voltage.
SYNCHRONIZING
Oscillator synchronization to an external input is achieved
by connecting a TTL logic-compatible square wave with a
duty cycle between
5%
and
75%
to the LT3435 SYNC pin.
The synchronizing range is equal to initial operating
frequency up to
700kHz
. This means that minimum
practical sync frequency is equal to the worst-case high
self-oscillating frequency (
575kHz
), not the typical oper-
ating frequency of
300kHz
. Caution should be used when
synchronizing above
575kHz
because at higher sync
frequencies the amplitude of the internal slope compen-
sation used to prevent subharmonic switching is re-
duced. This type of subharmonic switching only occurs at
input voltages less than twice output voltage. Higher
Figure 8. Undervoltage Lockout
inductor values will tend to eliminate this problem. See
Frequency Compensation section for a discussion of an
entirely different cause of subharmonic switching before
assuming that the cause is insufficient slope compensa-
tion. Application Note 19 has more details on the theory
of slope compensation.
If the FB pin voltage is below 0.9V (power-up or output
short-circuit conditions) the sync function is disabled.
This allows the frequency foldback to operate to avoid and
hazardous conditions for the SW pin.
If the synchronization signal is present during Burst Mode
operation, synchronization will occur during the burst
portion of the output waveform. Synchronizing the LT3435
during Burst Mode operation may alter the natural burst
frequency which can lead to jitter and increased ripple in
the burst waveform.
If no synchronization is required this pin should be con-
nected to ground.
POWER GOOD
The LT3435 contains a power good block which consists
of a comparator, delay timer and active low flag that allows
the user to generate a delayed signal after the power good
threshold is exceeded.
Referring to Figure 2, the PGFB pin is the positive input to
a comparator whose negative input is set at V
PGFB
. When
PGFB is taken above V
PGFB
, current (I
CSS
) is sourced into
the C
T
pin starting the delay period. When the voltage on
the PGFB pin drops below V
PGFB
the C
T
pin is rapidly
discharged resetting the delay period. The PGFB voltage is
typically generated by a resistive divider from the regu-
lated output or input supply.
The capacitor on the C
T
pin determines the amount of
delay time between the PGFB pin exceeding its threshold
(V
PGFB
) and the PG pin set to a high impedance state.
When the PGFB pin rises above V
PGFB
current is sourced
(I
CT
) from the C
T
pin into the external capacitor. When the
voltage on the external capacitor reaches an internal clamp
(V
CT
), the PG pin becomes a high impedance node. The
resultant PG delay time is given by t = C
CT
•(V
CT
)/(I
CT
). If
the voltage on the PGFB pin drops below its V
PGFB
, C
CT
will
be discharged rapidly and PG will be active low with a
200µA sink capability. If the SHDN pin is taken below its
APPLICATIO S I FOR ATIO
WUUU
ENABLE
1.3V
3435 F08
3µA
SHDN
R2
2.4V
–
+
SHDN
COMP
–
+
V
IN
COMP
15
V
IN
V
OUT
LT3435
4
R1
R3
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LT3435IFE#TRPBF

Mfr. #:
Buy LT3435IFE#TRPBF
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators 500kHz Version of LT3434 (200kHz)
Lifecycle:
New from this manufacturer.
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