1-299
ACT
™
1 Series FPGAs
ACT 1 Timing Characteristics (continued)
(Worst-Case Commercial Conditions)
Output Module Timing ‘–3’ Speed ‘–2’ Speed ‘–1’ Speed ‘Std’ Speed 3.3 V Speed
Parameter Description Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
TTL Output Module Timing
1
t
DLH
Data to Pad High 6.7 7.6 8.7 10.3 15.0 ns
t
DHL
Data to Pad Low 7.5 8.6 9.8 11.5 16.7 ns
t
ENZH
Enable Pad Z to High 6.6 7.5 8.6 10.2 14.8 ns
t
ENZL
Enable Pad Z to Low 7.9 9.1 10.4 12.2 17.7 ns
t
ENHZ
Enable Pad High to Z 10.0 11.6 13.1 15.4 22.4 ns
t
ENLZ
Enable Pad Low to Z 9.0 10.4 11.8 13.9 20.2 ns
d
TLH
Delta Low to High 0.06 0.07 0.08 0.09 0.13 ns/pF
d
THL
Delta High to Low 0.08 0.09 0.10 0.12 0.17 ns/pF
CMOS Output Module Timing
1
t
DLH
Data to Pad High 7.9 9.2 10.4 12.2 17.7 ns
t
DHL
Data to Pad Low 6.4 7.2 8.2 9.8 14.2 ns
t
ENZH
Enable Pad Z to High 6.0 6.9 7.9 9.2 13.4 ns
t
ENZL
Enable Pad Z to Low 8.3 9.4 10.7 12.7 18.5 ns
t
ENHZ
Enable Pad High to Z 10.0 11.6 13.1 15.4 22.4 ns
t
ENLZ
Enable Pad Low to Z 9.0 10.4 11.8 13.9 20.2 ns
d
TLH
Delta Low to High 0.10 0.11 0.13 0.15 0.22 ns/pF
d
THL
Delta High to Low 0.06 0.07 0.08 0.09 0.13 ns/pF
Notes:
1. Delays based on 35 pF loading.
2. SSO information can be found in the “Simultaneous Switching Output Limits for Actel FPGAs” application note on page 4-125.