A1020B-2PL44I Datasheet A1010B-2PLG68I, A1010B-2PLG68C, A1010B-1PL44C | P7-P9

1-289

ACT

™

1 Series FPGAs

Package Thermal Characteristics

The device junction to case thermal characteristics is

θjc, and the junction to ambient air characteristics is θja. The

thermal characteristics for

θja are shown with two different

air flow rates. Maximum junction temperature is 150°C.

A sample calculation of the maximum power dissipation for

an 84-pin plastic leaded chip carrier at commercial

temperature is as follows:

General Power Equation

P = [I

standby + I

active] * V

+ I

* V

* N + I

– V

) * M

Where:

standby is the current flowing when no inputs or

outputs are changing.

active is the current flowing due to CMOS switching.

, I

are TTL sink/source currents.

, V

are TTL level output voltages.

N equals the number of outputs driving TTL loads to

M equals the number of outputs driving TTL loads to

An accurate determination of N and M is problematical

because their values depend on the family type, design

details, and on the system I/O. The power can be divided into

two components: static and active.

Static Power Component

Actel FPGAs have small static power components that result

in lower power dissipation than PALs or PLDs. By integrating

multiple PALs/PLDs into one FPGA, an even greater

reduction in board-level power dissipation can be achieved.

The power due to standby current is typically a small

component of the overall power. Standby power is calculated

below for commercial, worst case conditions.

Power

3 mA 5.25 V 15.75 mW (max)

1 mA 5.25 V 5.25 mW (typ)

0.75 mA 3.60 V 2.70 mW (max)

0.30 mA 3.30 V 0.99 mW (typ)

Active Power Component

Power dissipation in CMOS devices is usually dominated by

the active (dynamic) power dissipation. This component is

frequency dependent, a function of the logic and the

external I/O. Active power dissipation results from charging

internal chip capacitances of the interconnect,

unprogrammed antifuses, module inputs, and module

outputs, plus external capacitance due to PC board traces

and load device inputs. An additional component of the active

power dissipation is the totem-pole current in CMOS

transistor pairs. The net effect can be associated with an

equivalent capacitance that can be combined with frequency

and voltage to represent active power dissipation.

Package Type Pin Count θjc

θja

Still Air

θja

300 ft/min Units

Plastic J-Leaded Chip Carrier

°C/W

Plastic Quad Flatpack 100 13 48 40 °C/W

Very Thin (1.0 mm) Quad Flatpack 80 12 43 35 °C/W

Ceramic Pin Grid Array 84 8 33 20 °C/W

Ceramic Quad Flatpack 84 5 40 30 °C/W

Max

junction

temp.

( )

Max

commercial

temp.

( )

–

C W

⁄( )

--------------------------------------------------------------------------------------------------------------------------------------------------

150

C 70

C–

C W

⁄

----------------------------------- 2.2

W= =

1-290

Equivalent Capacitance

The power dissipated by a CMOS circuit can be expressed by

the Equation 1.

Power (uW) = C

* V

CC2

* F (1)

Where:

is the equivalent capacitance expressed in pF.

is the power supply in volts.

F is the switching frequency in MHz.

Equivalent capacitance is calculated by measuring I

active

at a specified frequency and voltage for each circuit

component of interest. Measurements have been made over a

range of frequencies at a fixed value of V

. Equivalent

capacitance is frequency independent so that the results may

be used over a wide range of operating conditions. Equivalent

capacitance values are shown below.

Values for Actel FPGAs

To calculate the active power dissipated from the complete

design, the switching frequency of each part of the logic must

be known. Equation 2 shows a piece-wise linear summation

over all components.

Power = V

* [(m * C

EQM

* f

)

modules

(n * C

EQI

* f

)

inputs

+ (p * (C

EQO

+ C

) * f

)

outputs

0.5 * (q

* C

EQCR

* f

)

routed_Clk1

* f

)

routed_Clk1

] (2)

Where:

Fixed Capacitance Values for Actel FPGAs

(pF)

Device Type routed_Clk1

A1010B 41.4

A1020B 68.6

A10V10B 40

A10V20B 65

Determining Average Switching Frequency

To determine the switching frequency for a design, you must

have a detailed understanding of the data input values to the

circuit. The following guidelines are meant to represent

worst-case scenarios so that they can be generally used to

predict the upper limits of power dissipation. These

guidelines are as follows:

A10V10B

A10V20B

A1010B

A1020B

Modules (C

EQM

) 3.2 3.7

Input Buffers (

CEQI

) 10.9 22.1

Output Buffers (C

EQO

) 11.6 31.2

Routed Array Clock Buffer

Loads (C

EQCR

)

4.1 4.6

m = Number of logic modules switching at fm

n = Number of input buffers switching at fn

p = Number of output buffers switching at fp

= Number of clock loads on the first routed array

clock (All families)

= Fixed capacitance due to first routed array

clock (All families)

EQM

= Equivalent capacitance of logic modules in pF

EQI

= Equivalent capacitance of input buffers in pF

EQO

= Equivalent capacitance of output buffers in pF

EQCR

= Equivalent capacitance of routed array clock in

= Output lead capacitance in pF

= Average logic module switching rate in MHz

= Average input buffer switching rate in MHz

= Average output buffer switching rate in MHz

= Average first routed array clock rate in MHz (All

families)

Logic Modules (m) 90% of modules

Inputs switching (n) #inputs/4

Outputs switching (p) #outputs/4

First routed array clock loads (q

) 40% of modules

Load capacitance (C

) 35 pF

Average logic module switching rate (f

) F/10

Average input switching rate (f

) F/5

Average output switching rate (f

) F/10

Average first routed array clock rate

)

1-291

ACT

™

1 Series FPGAs

Functional Timing Tests

AC timing for logic module internal delays is determined

after place and route. The DirectTime Analyzer utility

displays actual timing parameters for circuit delays. ACT 1

devices are AC tested to a “binning” circuit specification.

The circuit consists of one input buffer + n logic modules +

one output buffer (n = 16 for A1010B; n = 28 for A1020B). The

logic modules are distributed along two sides of the device, as

inverting or non-inverting buffers. The modules are

connected through programmed antifuses with typical

capacitive loading.

Propagation delay [t

= (t

PLH

+ t

PHL

)/2] is tested to the

following AC test specifications.

Output Buffer Performance Derating (5V)

Note: The above curves are based on characterizations of sample devices and are not completely tested on all devices.

Output Buffer Performance Derating (3.3V)

Note: The above curves are based on characterizations of sample devices and are not completely tested on all devices.

Sink

0.2 0.3 0.4 0.5 0.6

(Volts)

(mA)

Source

–4

–6

–8

–10

–12

4.0 3.6 3.2 2.8 2.4

(Volts)

(mA)

2.0

Military, worst-case values at 125°C, 4.5 V.

Commercial, worst-case values at 70°C, 4.75 V.

Sink

0.0 0.1 0.2 0.3 0.4

(Volts)

(mA)

Source

–4

–6

–8

–10

–12

0 0.5 1.0 1.5 2.0

(Volts)

(mA)

2.5

Commercial, worst-case values at 70°C, 4.75 V.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24

A1020B-2PL44I

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IC FPGA 34 I/O 44PLCC

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