A1020B-PL68C Datasheet A1010B-2PLG68I, A1010B-2PLG68C, A1010B-1PL44C | P1-P3

April 1996

1-283

ACT

™

1 Series FPGAs

Features

• 5V and 3.3V Families fully compatible with JEDEC

specifications

• Up to 2000 Gate Array Gates (6000 PLD equivalent gates)

• Replaces up to 50 TTL Packages

• Replaces up to twenty 20-Pin PAL

Packages

• Design Library with over 250 Macro Functions

• Gate Array Architecture Allows Completely Automatic

Place and Route

• Up to 547 Programmable Logic Modules

• Up to 273 Flip-Flops

• Data Rates to 75 MHz

• Two In-Circuit Diagnostic Probe Pins Support Speed

Analysis to 25 MHz

• Built-In High Speed Clock Distribution Network

• I/O Drive to 10 mA (5 V), 6 mA (3.3 V)

• Nonvolatile, User Programmable

• Fabricated in 1.0 micron CMOS technology

Description

The ACT™ 1 Series of field programmable gate arrays

(FPGAs) offers a variety of package, speed, and application

combinations. Devices are implemented in silicon gate,

1-micron two-level metal CMOS, and they employ Actel’s

PLICE

antifuse technology. The unique architecture offers

gate array flexibility, high performance, and instant

turnaround through user programming. Device utilization is

typically 95 to 100 percent of available logic modules.

ACT 1 devices also provide system designers with unique

on-chip diagnostic probe capabilities, allowing convenient

testing and debugging. Additional features include an on-chip

clock driver with a hardwired distribution network. The

network provides efficient clock distribution with minimum

skew.

The user-definable I/Os are capable of driving at both TTL

and CMOS drive levels. Available packages include plastic

and ceramic J-leaded chip carriers, ceramic and plastic quad

flatpacks, and ceramic pin grid array.

A security fuse may be programmed to disable all further

programming and to protect the design from being copied or

reverse engineered.

Product Family Profile

The Designer and Designer

Advantage™ Systems

The ACT 1 device family is supported by Actel’s Designer and

Designer Advantage Systems, allowing logic design

implementation with minimum effort. The systems offer

Microsoft

Windows

™

and X Windows

™

graphical user

interfaces and integrate with the resident CAE system to

provide a complete gate array design environment: schematic

capture, simulation, fully automatic place and route, timing

verification, and device programming. The systems also

include the ACTmap

™

VHDL optimization and synthesis tool

and the ACTgen

™

Macro Builder, a powerful macro function

generator for counters, adders, and other structural blocks.

Device

A1010B

A10V10B

A1020B

A10V20B

Capacity

Gate Array Equivalent Gates

PLD Equivalent Gates

TTL Equivalent Packages

20-Pin PAL Equivalent Packages

1,200

3,000

2,000

6,000

Logic Modules 295 547

Flip-Flops (maximum) 147 273

Routing Resources

Horizontal Tracks/Channel

Vertical Tracks/Column

PLICE Antifuse Elements

112,000

186,000

User I/Os (maximum) 57 69

Packages: 44 PLCC

68 PLCC

100 PQFP

80 VQFP

84 CPGA

44 PLCC

68 PLCC

84 PLCC

100 PQFP

80 VQFP

84 CPGA

84 CQFP

Performance

5 V Data Rate (maximum)

3.3 V Data Rate (maximum)

75 MHz

55 MHz

75 MHz

55 MHz

Note:

See Product Plan on page 1-286 for package availability.

1-284

The systems are available for 386/486/Pentium

™

PC and for

™

and Sun

™

workstations and for running Viewlogic

Mentor Graphics

, Cadence

™

, OrCAD

™

, and Synopsys

design environments.

ACT 1 Device Structure

A partial view of an ACT 1 device (Figure 1) depicts four logic

modules and distributed horizontal and vertical interconnect

tracks. PLICE antifuses, located at intersections of the

horizontal and vertical tracks, connect logic module inputs

and outputs. During programming, these antifuses are

addressed and programmed to make the connections

required by the circuit application.

The ACT 1 Logic Module

The ACT 1 logic module is an 8-input, one-output logic circuit

chosen for the wide range of functions it implements and for

its efficient use of interconnect routing resources (Figure 2).

The logic module can implement the four basic logic

functions (NAND, AND, OR, and NOR) in gates of two, three,

or four inputs. Each function may have many versions, with

different combinations of active-low inputs. The logic module

can also implement a variety of D-latches, exclusivity

functions, AND-ORs, and OR-ANDs. No dedicated hardwired

latches or flip-flops are required in the array, since latches

and flip-flops may be constructed from logic modules

wherever needed in the application.

I/O Buffers

Each I/O pin is available as an input, output, three-state, or

bidirectional buffer. Input and output levels are compatible

with standard TTL and CMOS specifications. Outputs sink or

Figure 1 •

Partial View of an ACT 1 Device

Figure 2 •

ACT 1 Logic Module

1-285

ACT

™

1 Series FPGAs

source 10 mA at TTL levels. See Electrical Specifications for

additional I/O buffer specifications.

Device Organization

ACT 1 devices consist of a matrix of logic modules arranged in

rows separated by wiring channels. This array is surrounded

by a ring of peripheral circuits including I/O buffers,

testability circuits, and diagnostic probe circuits providing

real-time diagnostic capability. Between rows of logic

modules are routing channels containing sets of segmented

metal tracks with PLICE antifuses. Each channel has 22

signal tracks. Vertical routing is permitted via 13 vertical

tracks per logic module column. The resulting network allows

arbitrary and flexible interconnections between logic

modules and I/O modules.

Probe Pin

ACT 1 devices have two independent diagnostic probe pins.

These pins allow the user to observe any two internal signals

by entering the appropriate net name in the diagnostic

software. Signals may be viewed on a logic analyzer using

Actel’s Actionprobe

diagnostic tools. The probe pins can

also be used as user-defined I/Os when debugging is finished.

ACT 1 Array Performance

Temperature and Voltage Effects

Worst-case delays for ACT 1 arrays are calculated in the same

manner as for masked array products. A typical delay

parameter is multiplied by a derating factor to account for

temperature, voltage, and processing effects. However, in an

ACT 1 array, temperature and voltage effects are less

dramatic than with masked devices. The electrical

characteristics of module interconnections on ACT 1 devices

remain constant over voltage and temperature fluctuations.

As a result, the total derating factor from typical to

worst-case for a standard speed ACT 1 array is only 1.19 to 1,

compared to 2 to 1 for a masked gate array.

Logic Module Size

Logic module size also affects performance. A mask

programmed gate array cell with four transistors usually

implements only one logic level. In the more complex logic

module (similar to the complexity of a gate array macro) of

an ACT 1 array, implementation of multiple logic levels

within a single module is possible. This eliminates interlevel

wiring and associated RC delays. The effect is termed “net

compression.”

Ordering Information

Application (Temperature Range)

C = Commercial (0 to +70°C)

I = Industrial (–40 to +85°C)

M = Military (–55 to +125°C)

B = MIL-STD-883

Package Type

PL = Plastic J-Leaded Chip Carriers

PQ = Plastic Quad Flatpacks

CQ = Ceramic Quad Flatpack

PG = Ceramic Pin Grid Array

VQ = Very Thin Quad Flatpack

Speed Grade

Blank = Standard Speed

–1 = Approximately 15% faster than Standard

–2 = Approximately 25% faster than Standard

–3 = Approximately 35% faster than Standard

Part Number

A1010 = 1200 Gates (5 V)

A1020 = 2000 Gates (5 V)

A10V10 = 1200 Gates (3.3 V)

A10V20 = 2000 Gates (3.3 V)

Die Revision

B = 1.0 micron CMOS Process

Package Lead Count

A1010 B – 2 PL 84 C

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24

A1020B-PL68C

Mfr. #:

Buy A1020B-PL68C

Manufacturer:

Microchip / Microsemi

Description:

IC FPGA 57 I/O 68PLCC

Lifecycle:

New from this manufacturer.

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A1020B-PL68C

A1020B-PL68C

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