1-289
ACT
™
1 Series FPGAs
Package Thermal Characteristics
The device junction to case thermal characteristics is
θjc, and the junction to ambient air characteristics is θja. The
thermal characteristics for
θja are shown with two different
air flow rates. Maximum junction temperature is 150°C.
A sample calculation of the maximum power dissipation for
an 84-pin plastic leaded chip carrier at commercial
temperature is as follows:
General Power Equation
P = [I
CC
standby + I
CC
active] * V
CC
+ I
OL
* V
OL
* N + I
OH
*
(V
CC
– V
OH
) * M
Where:
I
CC
standby is the current flowing when no inputs or
outputs are changing.
I
CC
active is the current flowing due to CMOS switching.
I
OL
, I
OH
are TTL sink/source currents.
V
OL
, V
OH
are TTL level output voltages.
N equals the number of outputs driving TTL loads to
V
OL
.
M equals the number of outputs driving TTL loads to
V
OH
.
An accurate determination of N and M is problematical
because their values depend on the family type, design
details, and on the system I/O. The power can be divided into
two components: static and active.
Static Power Component
Actel FPGAs have small static power components that result
in lower power dissipation than PALs or PLDs. By integrating
multiple PALs/PLDs into one FPGA, an even greater
reduction in board-level power dissipation can be achieved.
The power due to standby current is typically a small
component of the overall power. Standby power is calculated
below for commercial, worst case conditions.
I
CC
V
CC
Power
3 mA 5.25 V 15.75 mW (max)
1 mA 5.25 V 5.25 mW (typ)
0.75 mA 3.60 V 2.70 mW (max)
0.30 mA 3.30 V 0.99 mW (typ)
Active Power Component
Power dissipation in CMOS devices is usually dominated by
the active (dynamic) power dissipation. This component is
frequency dependent, a function of the logic and the
external I/O. Active power dissipation results from charging
internal chip capacitances of the interconnect,
unprogrammed antifuses, module inputs, and module
outputs, plus external capacitance due to PC board traces
and load device inputs. An additional component of the active
power dissipation is the totem-pole current in CMOS
transistor pairs. The net effect can be associated with an
equivalent capacitance that can be combined with frequency
and voltage to represent active power dissipation.
Package Type Pin Count θjc
θja
Still Air
θja
300 ft/min Units
Plastic J-Leaded Chip Carrier
44
68
84
15
13
12
45
38
37
35
29
28
°C/W
°C/W
°C/W
Plastic Quad Flatpack 100 13 48 40 °C/W
Very Thin (1.0 mm) Quad Flatpack 80 12 43 35 °C/W
Ceramic Pin Grid Array 84 8 33 20 °C/W
Ceramic Quad Flatpack 84 5 40 30 °C/W
Max
junction
temp.
°
C
( )
Max
commercial
temp.
°
C
( )
–
θ
ja
°
C W
⁄( )
--------------------------------------------------------------------------------------------------------------------------------------------------
150
°
C 70
°
C–
37
°
C W
⁄
----------------------------------- 2.2
W= =