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HV9808PJ-G

P1-P3P4-P6P7-P7
Supertex inc.
Supertex inc.
www.supertex.com
Doc.# DSFP-HV9808
B032714
HV9808
Block Diagram
32-Channel Serial to Parallel Converter
With High Voltage Push-Pull Outputs
HV
OUT
1
HV
OUT
2
(Outputs 3 to 30
not shown)
HV
OUT
31
HV
OUT
32
POLARITY
BLANKING
LATCH ENABLE
DATA INPUT
CLOCK
DATA OUT
Latch
Latch
Latch
Latch
VPP
32-Bit
Shift
Register
Features
► Processed with HVCMOS
®
technology
► Output voltages up to 80V
► Low power level shifting
► Shift register speed 8.0MHz
► Latched data outputs
► 5.0V CMOS compatible inputs
► Forward and reverse shifting options
► Diode to VPP allows efcient power recovery
General Description
The HV9808 is a low voltage serial to high voltage parallel
converters with push-pull outputs. This device has been designed
for use as a driver for AC-electroluminescent displays.It can also
be used in any application requiring multiple output, high voltage
current sourcing and sinking capabilities such as driving plasma
panels, vacuum uorescent, or large matrix LCD displays. The
inputs are fully CMOS compatible.
This device consists of a 32-bit shift register, 32 latches, and
control logic to perform the polarity select and blanking of the
outputs. HV
OUT
1 is connected to the rst stage of the shift register
through the polarity and blanking logic. Data is shifted through
the shift register on the logic low to high transition of the clock.
The HV9808 shifts data in the counter-clockwise direction when
viewed from the top of the package. A data output buffer is
provided for cascading devices.This output reects the current
status of the last bit of the shift register (HV
OUT
32). Operation
of the shift register is not affected by the LE (latch enable), BL
(blanking), or the POL (polarity) in-puts. Transfer of data from the
shift register to the latch occurs when the LE (latch enable) input
is high. The data in the latch is stored when LE is low.
2
Supertex inc.
www.supertex.com
Doc.# DSFP-HV9808
B032714
HV9808
Absolute Maximum Ratings
Supply voltage, V
DD
-0.5V to +7.0V
Supply voltage, V
PP
-0.5V to +90V
Logic input levels -0.5V to V
DD
+0.5V
Ground current
1
1.5A
Continuous total power dissipation
2
1200mW
Operating temperature range -40°C to +85°C
Storage temperature range -65°C to +150°C
Parameter Value
Sym Parameter Min Max Units
Recommended Operating Conditions
V
DD
Logic voltage supply 4.5 5.5 V
V
PP
High voltage supply 8.0 80 V
V
IH
Input high voltage V
DD
-0.5 V
DD
V
V
IL
Input low voltage 0 0.5 V
f
CLK
Clock frequency 0 8.0 MHz
T
A
Operating free-air temperature -40 +85 °C
Notes:
1. Duty cycle is limited by the total power dissipated in the package.
2. For operation above 25°C ambient derate linearly to maximum operating
temperature at 20mW/°C.
Product Marking
Absolute Maximum Ratings are those values beyond which damage to the device
may occur. Functional operation under these conditions is not implied. Continuous
operation of the device at the absolute rating level may affect device reliability. All
voltages are referenced to device ground.
YY = Year Sealed
WW = Week Sealed
L = Lot Number
A = Assembler ID
C = Country of Origin*
= “Green” Packaging
*May be part of top marking
Top Marking
Bottom Marking
YYWW AAA
HV9808PJ
LLLLLLLLLL
CCCCCCCCCCC
44-Lead PLCC
Package may or may not include the following marks: Si or
Pin Conguration
1
44
6
40
44-Lead PLCC
Ordering Information
Part Number Package Packing
HV9808PJ-G 44-Lead PLCC 27/Tube
HV9808PJ-G M903 44-Lead PLCC 500/Reel
-G denotes a lead (Pb)-free / RoHS compliant package
Typical Thermal Resistance
Package θ
ja
44-Lead PLCC 37°C/W
Power-Up Sequence
1. Connect ground
2. Apply V
DD
3. Set all inputs (Data, CLK, Enable, etc.) to a known state
4. Apply V
PP
Power-down sequence should be the reverse of the above.
The V
PP
should not drop below V
DD
during operations.
3
Supertex inc.
www.supertex.com
Doc.# DSFP-HV9808
B032714
HV9808
Sym Parameter Min Max Units Conditions
Electrical Characteristics (V
PP
= 60V, V
DD
= 5.0V, T
A
= 25°C)
DC Characteristics
AC Characteristics
Sym Parameter Min Max Units Conditions
f
CLK
Clock frequency - 8.0 MHz ---
t
WL
or t
WH
Clock width, high or low 62 - ns ---
t
SU
Setup time before CLK rises 25 - ns ---
t
H
Hold time after CLK rises 10 - ns ---
t
DLH
(Data) Data output delay after L to H CLK - 110 ns CL = 15pF
t
DHL
(Data) Data output delay after H to L CLK - 110 ns CL = 15pF
t
DLE
LE delay after L to H CLK 50 - ns ---
t
WLE
Width of LE pulse 50 - ns ---
t
SLE
LE setup time before L to H CLK 50 - ns ---
t
ON
Delay from LE to HV
OUT
, L to H - 500 ns ---
t
OFF
Delay from LE to HV
OUT
, H to L - 500 ns ---
I
PP
V
PP
supply current - 100 µA HV
OUTPUTS
high to low
I
DDQ
I
DD
supply current (quiescent) - 100 µA All inputs = V
DD
or GND
I
DD
I
DD
supply current (operating) - 15 mA V
DD
= V
DD
max, f
CLK
= 8.0 MHz
V
OH
(Data) Shift register output voltage V
DD
-0.5 - V I
O
= -100µA
V
OL
(Data) Shift register output voltage - 0.5 V I
O
= 100µA
I
IH
Current leakage, any input - 1.0 µA Input = V
DD
I
IL
Current leakage, any input - -1.0 µA Input = GND
V
OC
HV output clamp diode voltage - -1.5 V I
OC
= -5.0mA
V
OH
HV output when sourcing 52 - V I
OH
= -20mA, 0 to 70°C
V
OL
HV output when sinking - 4.0 V I
OL
= 5.0mA, 0 to 70°C
Input and Output Equivalent Circuits
VDD
DATA IN
GND
VPP
GND
HVOUT
Logic Inputs
GND
DATA OUTPUT
Logic Data Output
High Voltage Outputs
VDD
P1-P3P4-P6P7-P7

HV9808PJ-G

Mfr. #:
Buy HV9808PJ-G
Manufacturer:
Microchip Technology
Description:
Counter Shift Registers 32CH W/HI-VOLT CMOS OUTPUT 80V
Lifecycle:
New from this manufacturer.
Delivery:
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