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X5083S8IZ-2.7
P1-P3
P4-P6
P7-P9
P10-P12
P13-P15
P16-P18
P19-P21
10
FN8127.4
November 12, 2015
01234567
CS
SI
SCK
High Impedance
SO
Instruction
(1 Byte)
FIGURE 7.
WREN/WRDI SEQUENCE
32
33
34
35
36
37
38
39
SCK
SI
CS
012
345
67
89
1
0
SCK
SI
Instruction
16 Bit Address
Data Byte 1
76
54
321
0
CS
40
41
42
43
44
45
46
47
Data Byte 2
76
543
210
Data Byte 3
765
432
10
Data Byte N
15
14
13
3
2
1
0
20
21
22
23
24
25
26
27
28
29
30
31
65
4
32
1
0
FIGURE 8.
EEPROM ARRA
Y WRITE SEQUENCE
0123456789
CS
SCK
SI
SO
High Impedance
Instruction
10
11
12
13
14
15
Data Byte
65
4
32
10
W
D
1
W
D
0
B
L
2
L
1
L
0
BB
FIGURE 9.
ST
A
T
US REGISTER WRITE SEQUENCE
X5083
11
FN8127.4
November 12, 2015
01234567
CS
SCK
SI
SO
SO MSB HIGH while
in the Nonvolati
le write cycle
01234567
READ STATUS
INST
RUCTION
READ STATUS
INSTRUCTION
SO MSB still HIGH i
ndicates
Nonvolatile writ
e cycle still i
n progress
01234567
CS
SCK
SI
SO
01234567
READ STATUS
INSTRUCTION
READ STATUS
INSTRUCTION
1st detected SO MSB LOW
indicates end of
Nonvolatile write cycle
43210
WD1
WD0
BL2
BL1
BL0
NONVOLA
TILE WRITE IN PROGRESS
NONVOLA
TILE
WRITE ENDS
FIGURE 10.
READ NONVOLA
TILE WR
ITE ST
A
TUS
X5083
12
FN8127.4
November 12, 2015
Symbol T
able
012345
CS
SCK
SI
INSTRUCTION
t
WC
Non-volatile
Writ
e
Operation
67
NEXT
Wait t
WC
after a write for new operation,
if not using polling pro
cedure
FIGURE 1
1.
END OF NONVOLA
TILE WRITE (N
O POLLING)
WAVEFORM
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from LOW
to HIGH
Will change
from LOW
to HIGH
May change
from HIGH
to LO
W
Will change
from HIGH
to LO
W
Don’t Care:
Changes
Allo
w
ed
Changing:
S
tate Not
Known
N/A
Center Line
is High
Impedance
X5083
P1-P3
P4-P6
P7-P9
P10-P12
P13-P15
P16-P18
P19-P21
X5083S8IZ-2.7
Mfr. #:
Buy X5083S8IZ-2.7
Manufacturer:
Renesas / Intersil
Description:
Supervisory Circuits CPU SUP/WDT 8K SPI EE RST LW 8LD COM
Lifecycle:
New from this manufacturer.
Delivery:
DHL
FedEx
Ups
TNT
EMS
Payment:
T/T
Paypal
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Union
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