LT3597
16
3597fa
applicaTions inForMaTion
Selecting the optimum switching frequency depends
on several factors. Inductor size is reduced with higher
frequency, but efficiency drops slightly due to higher
switching losses. Some applications require very low
duty cycles to drive a small number of LEDs from a high
supply. Low switching frequency allows a greater range
of operational duty cycle and hence a lower number of
LEDs can be driven. In each case, the switching frequency
can be tailored to provide the optimum solution. When
programming the switching frequency, the total power
losses within the IC should be considered.
Switching Frequency Synchronization
The nominal operating frequency of the LT3597 is pro-
grammed using a resistor from the RT pin to ground
over a 200kHz to 1MHz range. In addition, the internal
oscillator can be synchronized to an external clock applied
to the SYNC pin. The synchronizing clock signal input to
the LT3597 must have a frequency between 240kHz and
1MHz, a duty cycle between 20% and 80%, a low state
below 0.4V and a high state above 1.6V. Synchronization
signals outside of these parameters will cause erratic
switching behavior. For proper operation, an R
T
resistor
is chosen to program a switching frequency 20% slower
than the SYNC pulse frequency. Synchronization occurs
at a fixed delay after the rising edge of SYNC.
The SYNC pin must be grounded if the clock synchroniza-
tion feature is not used. When the SYNC pin is grounded,
the internal oscillator controls the switching frequency of
the converter.
Operating Frequency Trade-offs
Selection of the operating frequency is a trade-off between
efficiency, component size, output voltage and maximum
input voltage. The advantage of high frequency operation
is smaller component sizes and values. The disadvantages
are lower efficiency and lower input voltage range for a
desired output voltage. The highest acceptable switch-
ing frequency (f
SW(MAX)
) for a given application can be
calculated as follows:
f
SW(MAX)
=
V
D
V
OUT
t
ON(MIN)
V
D
+ V
IN
− V
SW
( )
Figure 11. Programming Maximum V
OUT1-3
where V
IN
is the typical input voltage, V
OUT
is the output
voltage, V
D
is the catch diode drop (0.5V) and V
SW
is the
internal switch drop (0.5V at max load). This equation
shows that slower switching is necessary to accommodate
high V
IN
/V
OUT
ratios. The reason the input voltage range
depends on the switching frequency is due to the finite
minimum switch on and off times. The switch minimum
on and off times are 200ns.
Adaptive Loop Control
The LT3597 uses an adaptive control mechanism to set
the buck output voltage. This control scheme ensures
maximum efficiency while not compromising minimum
PWM pulse widths. When PWM1-3 is low, the output of
the respective buck rises to a maximum value set by an
external resistor divider to the respective FB pin. Once
PWM1-3 goes high, the output voltage is adaptively re-
duced until the voltage across the LED current sink is 1V.
Figure 11 shows how the maximum output voltage can
be set by an external resistor divider.
LT3597
3597 F11
FB1-3
R2
R1
V
OUT1-3
V
OUT1-3
The maximum output voltage must be set to exceed the
maximum LED drop plus 1V by a margin greater than 10%.
However, this margin must not exceed a voltage of 10V.
This ensures proper adaptive loop control. The equations
below are used to estimate the resistor divider ratio. The
sum of the resistors should be less than 100k to avoid
noise coupling to the FB pin.
V
OUT(MAX)
= 1.1 V
LED(MAX)
+1.1V
( )
= 1.2V • 1+
R2
R1
V
OUT(MAX)
= V
LED(MAX)
+1.1V +V
MARGIN
V
MARGIN
≤ 10V
