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SAA7706H/N210,557

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P52
2001 Mar 05 22
Philips Semiconductors Product specification
Car radio Digital Signal Processor (DSP) SAA7706H
8.7.3 FUNCTION OF PIN POM
With pin POM it is possible to switch off the reference
current of the DAC. The capacitor on pin POM determines
the time after which this current has a soft switch-on. So at
power-on the current audio signal outputs are always
muted. The loading of the external capacitor is done in two
stages via two different current sources. The loading starts
at a current level that is lower than the current loading after
the voltage on pin POM has past a particular level. This
results in an almost dB-linear behaviour. This must
prevent ‘plop’ effects during power on or off.
8.7.4 POWER-OFF PLOP SUPPRESSION
To avoid plops in a power amplifier, the supply voltage of
the analog part of the DAC and the rest of the chip can be
fed from a separate power supply of 3.3 V. A capacitor
connected to this power supply enables to provide power
to the analog part at the moment the digital voltage is
switching off fast. In this event the output voltage will
decrease gradually allowing the power amplifier some
extra time to switch off without audible plops.
8.7.5 PIN VREFDA FOR INTERNAL REFERENCE
With two internal resistors half the supply voltage V
DDA2
is
obtained and used as an internal reference. This reference
voltage is used as DC voltage for the output operational
amplifiers and as reference for the DAC.
In order to obtain the lowest noise and to have the best
ripple rejection, a filter capacitor has to be added between
this pin and ground, preferably close to the analog
pin V
SSA2
.
8.7.6 SUPPLY OF THE FILTER STREAM DAC
The entire analog circuitry of the DACs and the operational
amplifiers are supplied by 2 supply pins: V
DDA2
and V
SSA2
.
V
DDA2
must have sufficient decoupling to prevent total
harmonic distortion degradation and to ensure a good
power supply rejection ratio. The digital part of the DAC is
fully supplied from the chip core supply.
8.8 Clock circuit and oscillator
The chip has an on-chip crystal clock oscillator. The block
diagram of this Pierce oscillator is shown in Fig.13. The
active element needed to compensate for the loss
resistance of the crystal is the block G
m
. This block is
placed between the external pins OSC_IN
and OSC_OUT. The gain of the oscillator is internally
controlled by the AGC block. A sine wave with a
peak-to-peak voltage close to the oscillator power supply
voltage is generated. The AGC block prevents clipping of
the sine wave and therefore the higher harmonics are as
low as possible. At the same time the voltage of the sine
wave is as high as possible which reduces the jitter going
from sine wave to the clock signal.
handbook, full pagewidth
MGT469
AGC
G
m
R
bias
C2
C1
clock to circuit
on-chip
off-chip
OSC_IN OSC_OUT
63 64
V
DD(OSC)
0.5V
DD(OSC)
V
SS(OSC)
65 62
Fig.13 Block diagram oscillator circuit.
2001 Mar 05 23
Philips Semiconductors Product specification
Car radio Digital Signal Processor (DSP) SAA7706H
handbook, full pagewidth
MGT470
AGC
G
m
R
bias
C2
C1
C3
clock to circuit
on-chip
off-chip
OSC_IN
slave input 3.3 V(p-p)
OSC_OUT
63 64
V
DD(OSC)
0.5V
DD(OSC)
V
SS(OSC)
65 62
Fig.14 Block diagram of the oscillator in slave mode.
8.8.1 SUPPLY OF THE CRYSTAL OSCILLATOR
The power supply connections of the oscillator are
separated from the other supply lines. This is done to
minimize the feedback from the ground bounce of the chip
to the oscillator circuit. Pin V
SS(OSC)
is used as ground
supply and pin V
DD(OSC)
as positive supply. A series
resistor plus capacitance is required for proper operating
on pin V
DD(OSC)
, see Figs 25 and 26. See also important
remark in Section 8.10.
8.9 The phase-locked loop circuit to generate the
DSPs and other clocks
There are several reasons why a PLL circuit is used to
generate the clock for the DSPs:
• The PLL makes it possible to switch in the rare cases
that tuning on a multiple of the DSP clock frequency
occurs to a slightly higher frequency for the clock of the
DSP. In this way an undisturbed reception with respect
to the DSP clock frequency is possible.
• Crystals for the crystal oscillator in the range of twice the
required DSP clock frequency, so approximately
100 MHz, are always third overtone crystals and must
also be manufactured on customer demand. This makes
these crystals expensive. The PLL1 enables the use of
a crystal running in the fundamental mode and also a
general available crystal can be chosen. For this circuit
a 256 × 44.1 kHz = 11.2896 MHzcrystal is chosen. This
type of crystal is widely used.
• Although a multiple of the frequency of the used crystal
of 11.2896 MHz falls within the FM reception band, this
will not disturb the reception because the relatively low
frequency crystal is driven in a controlled way and the
sine wave of the crystal has in the FM reception band
only very minor harmonics.
8.10 Supply of the digital part (V
DDD3V1
to V
DDD3V4
)
The supply voltage on pins V
DDD3V1
to V
DDD3V4
must be
for at least 10 ms earlier active than the supply voltage
applied to pin V
DD(OSC)
.
8.11 CL_GEN, audio clock recovery block
When an external I
2
S-bus or SPDIF source is connected,
the FSDAC circuitry needs an 256f
s
related clock. This
clock is recovered from either the incoming WS of the
digital serial input or the WS derived from the
SPDIF1/SPDIF2 input. There is also a possibility to
provide the chip with an external clock, in that case it must
be a 256f
s
clock with a fixed phase relation to the source.
2001 Mar 05 24
Philips Semiconductors Product specification
Car radio Digital Signal Processor (DSP) SAA7706H
8.12 External control pins
8.12.1 DSP1
For external control two input pins have been
implemented. The status of these pins can be changed by
applying a logic level. The status is saved in the DSP1
status register. The function of each pin depends on the
DSP1 program.
To control external devices two output pins are
implemented. The status of these pins is controlled by the
DSP program.
Function of these ‘control pins’ can be found in a separate
manual and is rom_code dependent.
8.12.2 DSP2
For external control four configurable I/O pins have been
implemented. Via the I
2
C-bus these four pins can be
independently configured as input or output. The status of
these pins can be changed by applying a logic level (input
mode). The status is saved in the DSP2 status register.
The function of each pin depends on the I
2
C-bus setting
and DSP2 program.
Function of these ‘control pins’ can be found in a separate
manual and is rom_code dependent.
8.13 I
2
C-bus control (pins SCL and SDA)
General information about the I
2
C-bus can be found in
“The I
2
C-bus and how to use it”
. This document can be
ordered using the code 9398 393 40011. For the external
control of the SAA7706H device a fast I
2
C-bus is
implemented. This is a 400 kHz bus which is
downward-compatible with the standard 100 kHz bus.
There are two different types of control instructions:
• Instructions to control the DSP program, programming
the coefficient RAM and reading the values of
parameters (level, multipath etc.)
• Instructions controlling the data flow; such as source
selection, IAC control and clock speed.
The detailed description of the I
2
C-bus and the description
of the different bits in the memory map is given in
Chapter 9.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P52

SAA7706H/N210,557

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Buy SAA7706H/N210,557
Manufacturer:
NXP Semiconductors
Description:
IC CAR RADIO DSP 80-QFP
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