Philips
Semiconductors
GTL16612
18-bit GTL/GTL
+
to LVTTL/TTL
bidirectional universal translator (3-State)
Product data
Supersedes data of 2000 Jun 19
2002 Dec 13
INTEGRATED CIRCUITS
Philips Semiconductors Product specification
GTL16612
18-bit GTL/GTL
+
to LVTTL/TTL bidirectional
universal translator (3-State)
2
2002 Dec 13
FEATURES
18-bit bidirectional bus interface
Translates between GTL/GTL+ logic levels (B ports) and
LVTTL/TTL logic levels (A ports)
5 V I/O tolerant on the LVTTL/TTL side (A ports)
No bus current loading when LVTTL/TTL output is tied to 5 V bus
3-State buffers
Output capability: +64 mA/-32 mA on the LVTTL/TTL side
(A ports); +40 mA on the GTL/GTL+ side (B ports)
TTL input levels on control pins
Power-up reset
Power-up 3-State
Positive edge triggered clock inputs
Latch-up protection exceeds 500 mA per JESD78
ESD protection exceeds 2000 V HBM per JESD22-A114,
200 V MM per JESD22-A115 and 1000 V CDM per JESD22-C101
DESCRIPTION
The GTL16612 is a high-performance BiCMOS product designed for
V
CC
operation at 3.3 V with I/O compatibility up to 5 V.
This device is an 18-bit universal transceiver featuring non-inverting
3-State bus compatible outputs in both send and receive directions.
Data flow in each direction is controlled by output enable (OEAB
and
OEBA
), latch enable (LEAB and LEBA), and clock (CPAB and
CPBA) inputs. For A-to-B data flow, the device operates in the
transparent mode when LEAB is High. When LEAB is Low, the A
data is latched if CPAB is held at a High or Low logic level. If LEAB
is Low, the A-bus data is stored in the latch/flip-flop on the
Low-to-High transition of CPAB. When OEAB
is Low, the outputs are
active. When OEAB
is High, the outputs are in the high-impedance
state. The clocks can be controlled with the clock-enable inputs
(CEBA
/CEAB).
Data flow for B-to-A is similar to that of A-to-B but uses OEBA
,
LEBA and CPBA.
QUICK REFERENCE DATA
CONDITIONS
TYPICAL
SYMBOL PARAMETER
CONDITIONS
T
amb
= 25 °C
3.3 V
UNIT
t
PLH
t
PHL
Propagation delay
An to Bn or Bn to An
C
L
= 50 pF 1.9 ns
C
IN
Input capacitance (Control pins) V
I
= 0 V or V
CC
4 pF
C
I/O
I/O pin capacitance Outputs disabled; V
I/O
= 0 V or V
CC
8 pF
I
CCZ
Total supply current Outputs disabled 12 mA
ORDERING INFORMATION
PACKAGES TEMPERATURE RANGE ORDER CODE DWG NUMBER
56-Pin Plastic SSOP -40 to +85 °C GTL16612DL SOT371-1
56-Pin Plastic TSSOP -40 to +85 °C GTL16612DGG SOT364-1
Standard packing quantities and other packaging data is available at www.philipslogic.com/packaging.
Philips Semiconductors Product specification
GTL16612
18-bit GTL/GTL
+
to LVTTL/TTL bidirectional
universal translator (3-State)
2002 Dec 13
3
PIN CONFIGURATION
GND
GND
CEAB
GND
LEAB
OEAB
GND
V
CC
NC
GND GND
V
CC
V
REF
GND
CEBA
GND
LEBA
OEBA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28 29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
CPAB
B0
B2
B1
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
CPBA
SW00485
A0
PIN DESCRIPTION
PIN NUMBER SYMBOL NAME AND FUNCTION
1, 27 OEAB/OEBA A-to-B/ B-to-A Output enable
input (active Low)
29, 56 CEBA/CEAB B-to-A/A-to-B clock enable
2, 28 LEAB/LEBA A-to-B/B-to-A Latch enable input
55,30 CPAB/CPBA A-to-B/B-to-A Clock input
(active rising edge)
3, 5, 6, 8, 9, 10,
12, 13, 14, 15,
16, 17, 19, 20,
21, 23, 24, 26
A0-A17 Data inputs/outputs (A side)
54, 52, 51, 49,
48, 47, 45, 44,
43, 42, 41, 40,
38, 37, 36, 34,
33, 31
B0-B17 Data inputs/outputs (B side)
4, 11, 18, 25,
32, 39, 46, 53
GND Ground (0 V)
7, 22 V
CC
Positive supply voltage
35 V
REF
GTL reference voltage
50 NC No connection

GTL16612DL,512

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
IC TRNSLTR BIDIRECTIONAL 56SSOP
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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