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NTQD6968NR2

P1-P3P4-P6P7-P7
NTQD6968N
http://onsemi.com
4
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
C, CAPACITANCE (pF)
Q
g
, TOTAL GATE CHARGE (nC)
V
GS
, GATE−TO−SOURCE VOLTAGE (VOLTS)
R
G
, GATE RESISTANCE (W)
V
SD
, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
I
S
, SOURCE CURRENT (AMPS)
t, TIME (ns)
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
I
D
, DRAIN CURRENT (AMPS)
100
10
1
0.1
0.01
1000
100
1
5
4
3
2
1
0
1.2
0.8
0.6
0.4
0.2
0
10
3000
2000
10
1500
1550
1000
500
0
5
Figure 7. Capacitance Variation Figure 8. Gate−to−Source Voltage
versus Total Charge
Figure 9. Resistive Switching Time Variation
versus Gate Resistance
Figure 10. Diode Forward Voltage versus
Current
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
Figure 12. Diode Reverse Recovery Waveform
20 0 52.5 7.5
1 10 100 0.5 0.525 0.6
0.1 10 1001
10
10 12.5
I
D
= 7.0 A
T
J
= 25°C
V
GS
V
GS
= 0 V
T
J
= 25°C
C
rss
C
iss
C
oss
C
rss
C
iss
V
GS
= 20 V
SINGLE PULSE
V
DD
= 16 V
I
D
= 7.0 A
V
GS
= 4.5 V
V
GS
= 0 V
T
J
= 25°C
t
r
t
d(off)
t
d(on)
t
f
R
DS(on)
Limit
Q
T
Q
2
Q
1
10 ms
1 ms
100 ms
dc
V
GS
V
DS
Thermal Limit
Package Limit
di/dt
t
rr
t
a
t
p
I
S
0.25 I
S
TIME
I
S
t
b
2500
V
DS
= 0 V
1
0.575
T
C
= 25°C
1.4
0.55
NTQD6968N
http://onsemi.com
5
10
0.001
0.0001
Figure 13. Thermal Response
t, TIME (s)
R(t), TRANSIENT THERMAL RESISTANCE (NORMALIZED)
0.000001 0.0001 0.001
1
0.01
10
0
1010.10.010.00001
D = 0.5
0.1
0.2
0.1
0.05
0.02
0.01
Single Pulse
NTQD6968N
http://onsemi.com
6
PACKAGE DIMENSIONS
TSSOP−8
CASE 948S−01
ISSUE A
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A 2.90 3.10 0.114 0.122
B 4.30 4.50 0.169 0.177
C −−− 1.10 −−− 0.043
D 0.05 0.15 0.002 0.006
F 0.50 0.70 0.020 0.028
G 0.65 BSC 0.026 BSC
L 6.40 BSC 0.252 BSC
M 0 8 0 8
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH. PROTRUSIONS OR GATE BURRS. MOLD
FLASH OR GATE BURRS SHALL NOT EXCEED
0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL NOT
EXCEED 0.25 (0.010) PER SIDE.
5. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
6. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
____
SEATING
PLANE
PIN 1
1
4
85
DETAIL E
B
C
D
A
G
L
2X L/2
−U−
S
U0.20 (0.008) T
S
U
M
0.10 (0.004) V
S
T
0.076 (0.003)
−T−
−V−
−W−
8x REFK
IDENT
K 0.19 0.30 0.007 0.012
S
U0.20 (0.008) T
P1
P
DETAIL E
F
M
0.25 (0.010)
K1
K
JJ1
SECTION N−N
J 0.09 0.20 0.004 0.008
K1 0.19 0.25 0.007 0.010
J1 0.09 0.16 0.004 0.006
P −−− 2.20 −−− 0.087
P1 −−− 3.20 −−− 0.126
N
N
mm
inches
0.038
0.95
0.252
6.4
0.018
0.45
0.026
0.65
0.177
4.5
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
P1-P3P4-P6P7-P7

NTQD6968NR2

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Manufacturer:
ON Semiconductor
Description:
MOSFET 20V 7A N-Channel
Lifecycle:
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