X9319WS8Z

7
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FN8185.3
July 31, 2014
For additional products, see www.intersil.com/en/products.html
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FIGURE 6. VOLTAGE REGULATOR FIGURE 7. OFFSET VOLTAGE ADJUSTMENT FIGURE 8. COMPARATOR WITH
HYSTERESIS
Basic Circuits (Continued)
R
1
R
2
I
adj
V
O
(REG) = 1.25V (1+R
2
/R
1
)+I
adj
R
2
V
O
(REG)V
IN
317
V
UL
= {R
1
/(R
1
+R
2
)} V
O
(max)
V
LL
= {R
1
/(R
1
+R
2
)} V
O
(min)
+
-
V
S
V
O
R
2
R
1
}
LT311A
}
X9319
8
FN8185.3
July 31, 2014
Submit Document Feedback
X9319
Package Outline Drawing
M8.15E
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
Rev 0, 08/09
Unless otherwise specified, tolerance : Decimal ± 0.05
The pin #1 identifier may be either a mold or mark feature.
Interlead flash or protrusions shall not exceed 0.25mm per side.
Dimension does not include interlead flash or protrusions.
Dimensions in ( ) for Reference Only.
Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3.
5.
4.
2.
Dimensions are in millimeters.1.
NOTES:
DETAIL "A"
SIDE VIEW “A
TYPICAL RECOMMENDED LAND PATTERN
TOP VIEW
A
B
4
4
0.25 AMC B
C
0.10 C
5
ID MARK
PIN NO.1
(0.35) x 45°
SEATING PLANE
GAUGE PLANE
0.25
(5.40)
(1.50)
4.90 ± 0.10
3.90 ± 0.10
1.27
0.43 ± 0.076
0.63 ±0.23
4° ± 4°
DETAIL "A"
0.22 ± 0.03
0.175 ± 0.075
1.45 ± 0.1
1.75 MAX
(1.27)
(0.60)
6.0 ± 0.20
Reference to JEDEC MS-012.
6.
SIDE VIEW “B”

X9319WS8Z

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
Digital Potentiometer ICs 100-TAP 10KOHMUP/DWN N/V 5V DCP-8
Lifecycle:
New from this manufacturer.
Delivery:
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