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MAX116EAX

P1-P3P4-P6P7-P9P10-P12P13-P14
MAX115/MAX116
2x4-Channel, Simultaneous-Sampling
12-Bit ADCs
4 _______________________________________________________________________________________
CONDITIONS UNITSMIN TYP MAXSYMBOLPARAMETER
I
OUT
= 1mA V4V
OH
Output High Voltage
I
OUT
= -1.6mA V0.4V
OL
Output Low Voltage
D0–D11 µA±10Three-State Leakage Current
pF10
Three-State Output
Capacitance
V4.75 5 5.25AV
DD
Positive Supply Voltage
V-5.25 -5 -4.75AV
SS
Negative Supply Voltage
V4.75 5 5.25DV
DD
Digital Supply Voltage
mA17 25I
AVDD
Positive Supply Current
mA-20 -15I
AVSS
Negative Supply Current
mA36Digital Supply Current
µA1Shutdown Positive Current
µA-1Shutdown Negative Current
µA13Shutdown Digital Current
(Note 10) LSB±1PSRR+Positive Supply Rejection
(Note 10) LSB±1PSRR-Negative Supply Rejection
(Note 11) mW175Power Dissipation
DIGITAL OUTPUTS (D0–D11, INT)
POWER REQUIREMENTS
ELECTRICAL CHARACTERISTICS (continued)
(AV
DD
= +5V ±5%, AV
SS
= -5V ±5%, DV
DD
= +5V ±5%, V
REFIN
= +2.5V (external reference), AGND = DGND = 0, 4.7µF capacitor
from REFOUT to AGND, 0.1µF capacitor from REFIN to AGND, f
CLK
= 16MHz, external clock, 50% duty cycle. T
A
= T
MIN
to T
MAX
,
unless otherwise noted. Typical values are at T
A
= +25°C.)
TIMING CHARACTERISTICS
(See Figure 4, AV
DD
= +5V, AV
SS
= -5V, DV
DD
= +5V, AGND = DGND = 0, T
A
= T
MIN
to T
MAX
, Typical values are at T
A
= +25°C,
unless otherwise noted.)
Guaranteed by design ns0t
CWS
CS to WR Setup Time
Guaranteed by design ns0t
CWH
CS to WR Hold Time
ns30t
WR
WR Low Pulse Width
ns30
CONDITIONS
t
AS
Address Setup Time
ns0t
AH
Address Hold Time
25pF load ns55t
ID
RD to INT Delay
ns45t
RD
Delay Time Between Reads
Guaranteed by design ns0t
CRS
CS to RD Setup Time
Guaranteed by design ns0t
CRH
CS to RD Hold Time
ns30t
RD
RD Low Pulse Width
25pF load (Note 12) ns40t
DA
Data-Access Time
25pF load (Note 13) ns545t
DH
Bus-Relinquish Time
ns30t
CW
CONVST Pulse Width
UNITSMIN TYP MAXSYMBOLPARAMETER
MAX115/MAX116
2x4-Channel, Simultaneous-Sampling
12-Bit ADCs
_______________________________________________________________________________________ 5
CONDITIONS UNITSMIN TYP MAXSYMBOLPARAMETER
TIMING CHARACTERISTICS (continued)
(See Figure 4, AV
DD
= +5V, AV
SS
= -5V, DV
DD
= +5V, AGND = DGND = 0, T
A
= T
MIN
to T
MAX
, Typical values are at T
A
= +25°C,
unless otherwise noted.)
Mode 1, Channel 1
µs
2
Mode 2, Channel 2 4
Mode 3, Channel 3 6
Mode 4, Channel 4 8
t
CONV
Exiting shutdown ms20Startup Time
Note 1: AV
DD
= +5V, AV
SS
= -5V, DV
DD
= +5V, V
REFIN
= 2.500V (external), V
IN
= ±5V (MAX115) or ±2.5V (MAX116).
Note 2: Integral nonlinearity is the analog value’s deviation at any code from its theoretical value after the full-scale range and
offset have been calibrated.
Note 3: CLK synchronized with CONVST.
Note 4: f
IN
= 10.06kHz, V
IN
= ±5V (MAX115) or ±2.5V (MAX116).
Note 5: First five harmonics.
Note 6: All inputs except CH1A driven with ±5V (MAX115) or ±2.5V (MAX116) 10.06kHz signal, CH1A connected to AGND and digi-
tized.
Note 7: AV
DD
= DV
DD
= +5V, AV
SS
= -5V, V
IN
= 0V (all channels).
Note 8: Temperature drift is defined as the change in output voltage from +25°C to T
MIN
or T
MAX
. It is calculated as
TC = [∆REFOUT/REFOUT] / ∆T.
Note 9: See Figure 2.
Note 10: Defined as the change in positive full scale caused by a ±5% variation in the nominal supply voltage. Tested with one input
at full scale and all others at AGND. V
REFIN
= +2.5V (internal).
Note 11: Tested with all inputs connected to AGND. V
REFIN
= +2.5V (internal).
Note 12: The data access time is defined as the time required for an output to cross +0.8V or +2.0V. It is measured using the circuit
of Figure 1. The measured number is then extrapolated back to determine the value with a 25pF load.
Note 13: The bus relinquish time is derived from the measured time taken for the data outputs to change +0.5V when loaded with the
circuit of Figure 1. The measured number is then extrapolated back to remove the effects of charging and discharging the
120pF capacitor. The time given is the part’s true bus relinquish time, which is independent of the external bus loading capac-
itance.
Conversion Time
Mode 1, Channel 1
ksps
390
Conversion Rate
Mode 2, Channel 2 218
Mode 3, Channel 3 152
Mode 4, Channel 4 116
_______________Detailed Description
The MAX115/MAX116 use a successive-approximation
conversion technique and four simultaneous-sampling
track/hold (T/H) amplifiers to convert analog signals into
12-bit digital outputs. Each T/H has two multiplexed
inputs, allowing a total of eight inputs. Each T/H output
is converted and stored in memory to be accessed
sequentially by the parallel interface with successive
read cycles. The MAX115/MAX116 internal micro-
sequencer can be programmed to digitize one, two,
three, or four inputs sampled simultaneously from either
of the two banks of four inputs (Figure 2). The
MAX115/MAX116 can operate with either an external or
internal clock. For internal operation, connect CLK to
DV
DD
.
MAX115/MAX116
2x4-Channel, Simultaneous-Sampling
12-Bit ADCs
6 _______________________________________________________________________________________
______________________________________________________________Pin Description
Figure 1. Load Circuit for Access Time and Bus Relinquish Time
TO OUTPUT
PIN
120pF
1.0mA
1.6mA
1.6V
Channel 3 Multiplexed Inputs (single-ended)CH3A, CH3B34, 35
Channel 4 Multiplexed Inputs (single-ended)CH4A, CH4B32, 33
Analog Supply VoltageAV
SS
31
Interrupt output. Falling edge indicates the end of a conversion sequence.
INT
30
Conversion-Start input. Rising edge initiates sampling and conversion sequence.
CONVST
29
Read Input (active-low)
RD
28
Write Input (active-low)
WR
27
Digital GroundDGND18
Data BitsD3, D219, 20
Bidirectional Data Bits/Address BitsD1/A3, D0/A221, 22
Clock Input (duty cycle must be 30% to 70%). Connect CLK to DV
DD
to activate internal clock.CLK25
Chip-Select Input (active-low)
CS
26
Reference-Buffer output. Bypass with a 4.7µF capacitor to AGND.REFOUT7
Analog ground. Both pins must be connected to ground.AGND8, 36
Data Bits. D11 = MSB.D11–D49–16
Digital Supply VoltageDV
DD
17
External reference input/internal reference output. Bypass with a 0.1µF capacitor to AGND.REFIN6
Analog Supply VoltageAV
DD
5
PIN
Channel 1 Multiplexed Inputs (single-ended)CH1B, CH1A3, 4
Channel 2 Multiplexed Inputs (single-ended)CH2B, CH2A1, 2
FUNCTIONNAME
Address BitsA1, A023, 24
P1-P3P4-P6P7-P9P10-P12P13-P14

MAX116EAX

Mfr. #:
Buy MAX116EAX
Manufacturer:
Maxim Integrated
Description:
Analog to Digital Converters - ADC 2x4-Channel, Simultaneous-Sampling 12-Bit ADCs
Lifecycle:
New from this manufacturer.
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