Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Dual DMOS Full-Bridge
Microstepping PWM Motor Driver
A3972
4
ELECTRICAL CHARACTERISTICS at T
A
= +25°C, V
BB
= 50 V, V
DD
= 5.0 V, V
S
= 0.5 V,
f
PWM
< 50 kHz (unless otherwise noted).
Limits
Characteristic Symbol Test Conditions Min. Typ. Max. Units
Load Supply Voltage Range V
BB
Operating 15 — 50 V
During sleep mode 0 50 V
Logic Supply Voltage Range V
DD
Operating 4.5 5.0 5.5 V
Load Supply Current I
BB
f
PWM
< 50 kHz 8.0 mA
Operating, outputs disabled 6.0 mA
Sleep or idle mode 20 μA
Logic Supply Current I
DD
f
PWM
< 50 kHz 12 mA
Outputs off 10 mA
Idle mode (D0 = 1, D18 = 0) 1.5 mA
Sleep mode 100 μA
Output Drivers
Output Leakage Current I
DSS
V
OUT
= V
BB
<1.0 50 μA
V
OUT
= 0 V <-1.0 -50 μA
Output On Resistance r
DS(on)
Source driver, I
OUT
= –1.5 A 0.5 0.55
Sink driver, I
OUT
= 1.5 A 0.315 0.35
Body Diode Forward Voltage V
F
Source diode, I
F
= 1.5 A 1.2 V
Sink diode, I
F
= 1.5 A 1.2 V
Control Logic
Logic Input Voltage V
IN(1)
2.0 V
V
IN(0)
0.8 V
Logic Input Current I
IN(1)
V
IN
= 2.0 V <1.0 20 μA
I
IN(0)
V
IN
= 0.8 V <-2.0 -20 μA
OSC Input Frequency Range f
OSC
Divide by one 2.5 6.0 MHz
(D0 =1, D13 = 0, D14 = 1)
OSC Input Duty Cycle 40 60 %
Input Hysterisis V
IN
0.20 — 0.40 V
continued next page ...
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Dual DMOS Full-Bridge
Microstepping PWM Motor Driver
A3972
5
ELECTRICAL CHARACTERISTICS at T
A
= +25°C, V
BB
= 50 V, V
DD
= 5.0 V, V
S
= 0.5 V,
f
PWM
< 50 kHz (unless otherwise noted).
Limits
Characteristics Symbol Test Conditions Min. Typ. Max. Units
Control Logic (continued)
Internal Oscillator f
OSC
OSC shorted to ground 3.0 4.0 5.0 MHz
R
OSC
= 51 k 3.4 4.0 4.6 MHz
DAC Accuracy (total error) E
T
Relative to DAC reference buffer
— ±1/2 — LSB
output, D0 = 0, D17 = 0
Reference Input Voltage Range V
REF(EXT)
0.5 — 2.6 V
Reference Buffer Offset V
OS
— ±10 — mV
Reference Divider Ratio V
REF
/V
S
D0 = 0, D18 = 0 8.0
D0 = 0, D18 = 1 4.0
Reference Input Current I
REF
V
REF
= 2.0 V ±0.5 μA
Internal Reference Voltage V
REF(INT)
1.94 2.0 2.06 V
Gain (G
m
) Error (note 3) E
G
D0 = 0, D17 = 0,
D18 = 0, DAC = 63 0 ±6 %
D18 = 0, DAC = 31 0 ±9 %
D18 = 1, DAC = 63 0 ±6 %
D18 = 1, DAC = 15 0 ±10 %
Comparator Input Offset Voltage V
IO
V
REF
= 0 V ±5.0 mV
Propagation Delay Times t
pd
50% to 90%:
PWM change to source on 500 800 1200 ns
PWM change to source off 50 150 350 ns
PWM change to sink on 500 800 1200 ns
PWM change to sink off 50 150 350 ns
Crossover Dead Time t
dt
300 700 900 ns
Thermal Shutdown Temperature T
J
— 165 — °C
Thermal Shutdown Hysteresis T
J
— 15 — °C
UVLO Enable Threshold V
UVLO
Increasing V
DD
3.9 4.2 4.45 V
UVLO Hysteresis V
UVLO
0.05 0.10 V
NOTES: 1. Typical Data is for design information only.
2. Negative current is de ned as coming out of (sourcing) the speci ed device terminal.
3. E
G
= [(V
REF
/Range) – V
S
]/(V
REF
/Range).
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Dual DMOS Full-Bridge
Microstepping PWM Motor Driver
A3972
6
Serial Interface. The A3972SB is controlled via a 3-wire
(clock, data, strobe) serial port. The programmable functions
allow maximum exibility in con guring the PWM to the motor
drive requirements. The serial data is written as two
19-bit words: 1 bit to select the word and 18 bits of data. The
serial data is clocked in starting with D18.
Word 0 Bit Assignments
Bit Function
D0 Word select = 0
D1 Bridge 1, DAC, LSB
D2 Bridge 1, DAC, bit 2
D3 Bridge 1, DAC, bit 3
D4 Bridge 1, DAC, bit 4
D5 Bridge 1, DAC, bit 5
D6 Bridge 1, DAC, MSB
D7 Bridge 2, DAC, LSB
D8 Bridge 2, DAC, bit 2
D9 Bridge 2, DAC, bit 3
D10 Bridge 2, DAC, bit 4
D11 Bridge 2, DAC, bit 5
D12 Bridge 2, DAC, MSB
D13 Bridge 1 phase
D14 Bridge 2 phase
D15 Bridge 1 mode
D16 Bridge 2 mode
D17 REF select
D18 Range select
D1 – D6 Bridge 1 Linear DAC. Six-bit word sets desired
current level for Bridge 1. Setting all six bits to zero disables
Bridge 1, with all drivers off (See current regulation section of
functional description).
D7 – D12 Bridge 2 Linear DAC. Six-bit word sets desired
current level for Bridge 2. Setting all six bits to zero disables
Bridge 2, with all drivers off (See current regulation section of
functional description).
FUNCTIONAL DESCRIPTION
continued next page ...
D13 Bridge 1 Phase. This bit controls the direction of output
current for Load 1.
D13 OUT
1A
OUT
1B
0 L H
1 H L
D14 Bridge 2 Phase. This bit controls the direction of output
current for Load 2.
D14 OUT
2A
OUT
2B
0 L H
1 H L
D15 Bridge 1 Mode.
D15 Mode
0 Mixed-decay
1 Slow-decay
D16 Bridge 2 Mode.
D16 Mode
0 Mixed-decay
1 Slow-decay
D17 REF Select. This bit determines the reference input for
the 6-bit linear DACs.
D17 Reference Voltage
0 Internal 2 V
1 External (3 V max)
D18 G
m
Range Select. This bit determines the scaling factor
(4 or 8) used.
D18 Divider Load Current
0 1/8 I
TRIP
= V
DAC
/8R
S
1 1/4 I
TRIP
= V
DAC
/4R
S

A3972SB

Mfr. #:
Manufacturer:
Description:
IC MTR DRV BIPOLR 4.5-5.5V 24DIP
Lifecycle:
New from this manufacturer.
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