LTC2944CDD#PBF Datasheet LTC2944CDD#TRPBF, LTC2944IDD#TRPBF, LTC2944IDD#PBF | P16-P18

LTC2944

2944f

For more information www.linear.com/LTC2944

Each device on the I

C/SMbus is recognized by a unique

address stored in that device and can operate as either a

transmitter or receiver, depending on the function of the

device. In addition to transmitters and receivers, devices

can also be classified as masters or slaves when perform

ing data

transfers. A master is the device which initiates a

data transfer on

the bus and generates the clock signals to

permit that transfer. At the same time any device addressed

is considered a slave. The LTC2944 always acts as a slave.

Figure 5 shows an overview of the data transmission on

the I

C bus.

Start and Stop Conditions

When the bus is idle, both SCL and SDA must be high. A

bus master signals the beginning of a transmission with

a START condition by transitioning SDA from high to low

while SCL is high. When the master has finished com

municating with the slave, it issues a STOP condition by

transitioning SDA from low to high while SCL is high. The

bus is then free for another transmission. When the bus

is in use, it stays busy if a repeated START (Sr) is gener

ated instead of a STOP condition. The repeated START

(Sr) conditions are

functionally identical to the START (S).

Write Protocol

The master begins a write operation with a START condition

followed by the seven bit slave address 1100100 and the

R/W bit set to zero, as shown in Figure 6. The LTC2944

acknowledges this by pulling SDA low and the master

sends a command byte which indicates which internal

and latches the command byte into its internal register

address pointer. The master delivers the data byte, the

LTC2944 acknowledges once more and latches the data

applicaTions inForMaTion

SCL

SDA

START

CONDITION

STOP

CONDITION

ADDRESS R/W ACK DATA ACK DATA ACK

1 - 7 8 9

2944 F05

a6 - a0 b7 - b0 b7 - b0

1 - 7 8 9 1 - 7 8 9

Figure 5. Data Transfer Over I

C or SMBus

2944 F04

INTEGRATOR

OUTPUT

REFHI

REFLO

TIME

WITH OFFSET

WITHOUT OFFSET

FASTER

UP RAMPING

SLOWER

DOWN RAMPING

For input signals with an absolute value smaller than the

offset of the internal op amp the LTC2944 stops integrat-

ing and does not integrate its own offset.

C/SMBus Interface

The LTC2944 communicates with a bus master using

a 2-wire interface compatible with I

C and SMBus. The

7-bit hard coded I

C address of the LTC2944 is 1100100.

The LTC2944 is a slave only device. The serial clock line

(SCL) is input only while the serial data line (SDA) is

bidirectional. The device supports I

C standard and fast

mode. For more details refer to the I

C Protocol section.

C Protocol

The LTC2944 uses an I

C/SMBus-compatible 2-wire

interface supporting multiple devices on a single bus.

Connected devices can only pull the bus lines low and

must never drive the bus high. The bus wires are externally

connected to a positive supply voltage via current sources

or pull-up resistors.

When the bus is idle, all bus lines

are high. Data on the I

C bus can be transferred at rates

of up to 100kbit/s in standard mode and up to 400kbit/s

in fast mode.

Figure 4. Offset Cancellation

LTC2944

2944f

For more information www.linear.com/LTC2944

FROM MASTER TO SLAVE

S W

ADDRESS REGISTER DATA

FROM SLAVE TO MASTER

2944 F06

A: ACKNOWLEDGE (LOW)

A: NOT ACKNOWLEDGE (HIGH)

S: START CONDITION

P: STOP CONDITION

R: READ BIT (HIGH)

W: WRITE BIT (LOW)

A A A

1100100 01h FCh

0 0 0

Figure 6. Writing FCh to the LTC2944 Control Register (B)

into the desired register. The transmission is ended when

the master sends a STOP condition. If the master contin-

ues by

sending a second data byte instead of a stop, the

LTC2944 acknowledges again,

increments its address

pointer and latches the second data byte in the following

applicaTions inForMaTion

Read Protocol

The master begins a read operation with a START condition

followed by the seven bit slave address 1100100 and the

R/W bit set to zero, as shown in Figure 8. The LTC2944

acknowledges and the master sends a command byte

which indicates which internal register the master is to

read. The LTC2944 acknowledges and then latches the

S W

ADDRESS REGISTER DATA

2944 F07

A A A

1100100 02h F0h 01h

0 0 0

DATA

S W

ADDRESS REGISTER Sr

2944 F08

A A ADDRESS

1100100 00h 1

0 0 1100100

01h

DATA

S W

ADDRESS REGISTER Sr

2944 F09

A A ADDRESS

1100100 08h 1

0 0 1100100

F1h

DATA

24h

DATA

command byte into its internal register address pointer.

The master then sends a repeated START condition fol-

lowed by

the same seven bit address with the R/W bit

now set to

one. The LTC2944 acknowledges and sends

the contents of the requested register. The transmission

is ended when the master sends a STOP condition. If

the master acknowledges the transmitted data byte, the

LTC2944 increments its address pointer and sends the

contents of the following register as depicted in Figure 9.

Alert Response Protocol

In a system where several slaves share a common inter

rupt line, the master can use the alert response address

(ARA) to determine which device initiated the interrupt

(Figure 10).

The master initiates the ARA procedure with a START

condition and the special 7-bit ARA bus address (0001100)

followed by the read bit (R) = 1. If the LTC2944 is as

serting the ALCC pin in alert mode, it acknowledges and

responds by sending its 7-bit bus address (1100100)

and a 0. While it is sending its address, it monitors the

SDA pin to see if another device is sending an address at

the same time using standard I

C bus arbitration. If the

LTC2944 is sending a 1 and reads a 0 on the SDA pin on

the

rising edge of SCL, it assumes another device with a

lower address is sending and the LTC2944 immediately

aborts its transfer and waits for the next ARA cycle to try

again. If transfer is successfully completed, the LTC2944

will stop pulling down the ALCC pin and will not respond

to further ARA requests until a new Alert event occurs.

Figure 7. Writing F001h to the LTC2944 Accumulated Charge

Figure 8. Reading the LTC2944 Status Register (A)

Figure 9. Reading the LTC2944 Voltage Register (I, J)

LTC2944

2944f

For more information www.linear.com/LTC2944

Preventing Violation of Absolute Maximum Ratings

The small size, robustness and low impedance of ceramic

capacitors make them an attractive option for the supply

bypass capacitor of LTC2944. However, these capacitors

can cause problems if the LTC2944 is plugged into a live

supply close to its maximum voltage of 65V. The low

loss ceramic capacitor, combined with stray inductance

in series with the power source, forms an under damped

tank circuit, and the voltage at the SENSE

–

pin of the

LTC2944 can ring several tens of volts, possibly exceed-

ing the

LTC2944 rating and damaging the part. This can

be prevented by

adding a transient voltage suppression

diode to the SENSE

–

pin as shown in Figure 14.

Also pulling the digital communication pins SCL, SDA and

ALCC below their minimum absolute maximum voltage

of –0.3V—for example, due to differences between the

local GND and the GND of the connected microproces

sor—increases the

supply current

of the LTC2944. At

supply voltages above 50V, the power dissipated due

to the increased supply current might damage the part,

which can be prevented by adding Schottky diodes as

shown in Figure 14.

S R

ALERT RESPONSE ADDRESS DEVICE ADDRESS

2944 F10

0001100 11001000

0 1

S W

ADDRESS REGISTER S

2944 F11

A A ADDRESS

1100100 02h 1

0 0 1100100

80h

DATA

01h

DATA

PC Board Layout Suggestions

Keep all traces as short as possible to minimize noise and

inaccuracy. Use a 4-wire Kelvin sense connection for the

sense resistor, locating the LTC2944 close to the resistor

with short sense-traces to the SENSE

and SENSE

–

pins.

Use wider traces from the resistor to the battery, load

and/or charger. Put the bypass capacitor close to SENSE

and GND.

applicaTions inForMaTion

Figure 10. LTC2944 Serial Bus SDA Alert Response Protocol

Figure 11. Reading the LTC2944 Accumulated Charge

Registers (C, D)

Figure 13. Kelvin Connection on Sense Resistor

Figure 12. ADC Single Conversion Sequence and Reading

of Voltage Registers (I,J)

40ms

S W

ADDRESS REGISTER S

2944 F12

A A ADDRESS

1100100 08h 1

0 0 1100100

F1h

DATA

80h

DATA

S W

ADDRESS REGISTER DATA

A A

1100100 01h 4C

0 0

2944 F13

LTC2944

SENSE

TO BATTERY

CHARGER/LOAD

CHARGER

2k2k 2k

LOAD

SENSE

50mΩ

MULTICELL

Li-ION

SMAJ58ACMHSHS-2L

2944 F14

1µF

3.3V

µP

SENSE

ALCC

SDA

SCL

LTC2944

GND

SENSE

–

Figure 14. Preventing Violation of Absolute Maximum Ratings

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P20

LTC2944CDD#PBF

Mfr. #:

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Battery Management 60V Battery Gas Gauge with Voltage, Current & Temperature Measurement

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LTC2944CDD#PBF

LTC2944CDD#PBF

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