TPN3R704PL,L1Q Datasheet TPN3R704PL,L1Q | P1-P3

TPN3R704PL

1

MOSFETs Silicon N-channel MOS (U-MOS-H)

TPN3R704PL

Start of commercial production

2015-10

1.

1. Applications

Applications

• High-Efficiency DC-DC Converters

• Switching Voltage Regulators

• Motor Drivers

2.

2. Features

Features

(1) High-speed switching

(2) Small gate charge: Q

SW

= 8.1 nC (typ.)

(3) Small output charge: Q

oss

= 20.2 nC (typ.)

(4) Low drain-source on-resistance: R

DS(ON)

= 3.0 mΩ (typ.) (V

GS

= 10 V)

(5) Low leakage current: I

DSS

= 10 µA (max) (V

DS

= 40 V)

(6) Enhancement mode: V

th

= 1.4 to 2.4 V (V

DS

= 10 V, I

D

= 0.2 mA)

3.

3. Packaging and Internal Circuit

Packaging and Internal Circuit

TSON Advance

1, 2, 3: Source

4: Gate

5, 6, 7, 8: Drain

2016-10-03

Rev.2.0

TPN3R704PL

2

4.

4. Absolute Maximum Ratings (Note) (T

Absolute Maximum Ratings (Note) (T

a

= 25

= 25 



 unless otherwise specified)

unless otherwise specified)

Characteristics

Drain-source voltage

Gate-source voltage

Drain current (DC)

Drain current (pulsed)

Power dissipation

Single-pulse avalanche energy

Single-pulse avalanche current

Channel temperature

Storage temperature

(T

c

= 25 )

(Silicon limit)

(t = 100 µs)

(T

c

= 25 )

(Note 1), (Note 2)

(Note 1)

(Note 3)

(Note 4)

(Note 5)

Symbol

V

DSS

V

GSS

I

D

I

D

I

DP

P

D

P

D

P

D

E

AS

I

AS

T

ch

T

stg

Rating

40

±20

80

92

200

86

2.67

0.63

10

80

175

-55 to 175

Unit

V

A

W

mJ

A



Note: Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the

significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even

if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum

ratings.

Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook

("Handling Precautions"/"Derating Concept and Methods") and individual reliability data (i.e. reliability test

report and estimated failure rate, etc).

5.

5. Thermal Characteristics

Thermal Characteristics

Characteristics

Channel-to-case thermal resistance

Channel-to-ambient thermal resistance

(T

c

= 25 )

(T

a

= 25 )

(T

a

= 25 )

(Note 3)

(Note 4)

Symbol

R

th(ch-c)

R

th(ch-a)

R

th(ch-a)

Max

1.73

56

235

Unit

/W

Note 1: Ensure that the channel temperature does not exceed 175 .

Note 2: Limited by package limit. Silicon chip capability is 92 A. (T

c

= 25 )

Note 3: Device mounted on a glass-epoxy board (a), Figure 5.1

Note 4: Device mounted on a glass-epoxy board (b), Figure 5.2

Note 5: V

DD

= 32 V, T

ch

= 25  (initial), L = 1.3 µH, I

AS

= 80 A

Fig.

Fig. 5.1

5.1

5.1 Device Mounted on a Glass-Epoxy

Device Mounted on a Glass-Epoxy

Board (a)

Fig.

Fig. 5.2

5.2

5.2 Device Mounted on a Glass-Epoxy

Device Mounted on a Glass-Epoxy

Board (b)

Note: This transistor is sensitive to electrostatic discharge and should be handled with care.

2016-10-03

Rev.2.0

TPN3R704PL

3

6.

6. Electrical Characteristics

Electrical Characteristics

6.1.

6.1. Static Characteristics (T

Static Characteristics (T

a

= 25

= 25 



 unless otherwise specified)

unless otherwise specified)

Characteristics

Gate leakage current

Drain cut-off current

Drain-source breakdown voltage

Gate threshold voltage

Drain-source on-resistance

Symbol

I

GSS

I

DSS

V

(BR)DSS

V

(BR)DSX

V

th

R

DS(ON)

Test Condition

V

GS

= ±20 V, V

DS

= 0 V

V

DS

= 40 V, V

GS

= 0 V

I

D

= 10 mA, V

GS

= 0 V

I

D

= 10 mA, V

GS

= -20 V

V

DS

= 10 V, I

D

= 0.2 mA

V

GS

= 4.5 V, I

D

= 13 A

V

GS

= 10 V, I

D

= 40 A

Min



40

25

1.4



Typ.



4.2

3.0

Max

±0.1

10



2.4

6.0

3.7

Unit

µA

V

mΩ

6.2.

6.2. Dynamic Characteristics (T

Dynamic Characteristics (T

a

= 25

= 25 



 unless otherwise specified)

unless otherwise specified)

Characteristics

Input capacitance

Reverse transfer capacitance

Output capacitance

Gate resistance

Switching time (rise time)

Switching time (turn-on time)

Switching time (fall time)

Switching time (turn-off time)

Symbol

C

iss

C

rss

C

oss

r

g

t

r

t

on

t

f

t

off

Test Condition

V

DS

= 20 V, V

GS

= 0 V, f = 1 MHz



See Fig. 6.2.1

Min



Typ.

1910

41

470

0.9

5.3

14.7

6.2

24

Max

2500

80



1.4



Unit

pF

Ω

ns

V

DD

≈ 20 V

V

GS

= 0 V/ 10 V

I

D

= 40 A

R

L

= 0.5 Ω

R

GG

= 4.7 Ω

R

GS

= 4.7 Ω

Duty ≤ 1 %, t

w

= 10 µs

Fig.

Fig. 6.2.1

6.2.1

6.2.1 Switching Time Test Circuit

Switching Time Test Circuit

6.3.

6.3. Gate Charge Characteristics (T

Gate Charge Characteristics (T

a

= 25

= 25 



 unless otherwise specified)

unless otherwise specified)

Characteristics

Total gate charge (gate-source plus

gate-drain)

Gate-source charge 1

Gate-drain charge

Gate switch charge

Output charge

Symbol

Q

g

Q

gs1

Q

gd

Q

SW

Q

oss

Test Condition

V

DD

≈ 20 V, V

GS

= 10 V, I

D

= 40 A

V

DD

≈ 20 V, V

GS

= 4.5 V, I

D

= 13 A

V

DD

≈ 20 V, V

GS

= 10 V, I

D

= 40 A

V

DS

= 20 V, V

GS

= 0 V

Min



Typ.

27

13.3

7.7

4.2

8.1

20.2

Max



Unit

nC

6.4.

6.4. Source-Drain Characteristics (T

Source-Drain Characteristics (T

a

= 25

= 25 



 unless otherwise specified)

unless otherwise specified)

Characteristics

Reverse drain current (pulsed)

Diode forward voltage

Reverse recovery time

Reverse recovery charge

(Note 6)

Symbol

I

DRP

(t = 100 µs)

V

DSF

t

rr

Q

rr

Test Condition



I

DR

= 80 A, V

GS

= 0 V

V

R

= 20 V, I

DR

= 20 A, V

GS

= 0

V, -dI

DR

/dt = 100 A/µs

Min



Typ.



28

18.2

Max

200

-1.2



Unit

A

V

ns

nC

Note 6: Ensure that the channel temperature does not exceed 175 .

2016-10-03

Rev.2.0

TPN3R704PL,L1Q

TPN3R704PL,L1Q

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