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MPC9352FA

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16
Advanced Clock Drivers Devices
Freescale Semiconductor 7
MPC9352
PACKAGE DIMENSIONS
Table 8. AC Characteristics (V
CC
= 2.5 V ± 5%, T
A
= –40° to 85°C)
(1)
1. AC characteristics apply for parallel output termination of 50 Ω to V
TT
.
Symbol Characteristics Min Typ Max Unit Condition
f
ref
Input reference frequency in PLL mode
(2)
÷4 feedback
÷6 feedback
÷8 feedback
÷12 feedback
Input reference frequency in PLL bypass mode
(3)
2. PLL mode requires PLL_EN=0 to enable the PLL and zero-delay operation. It is not recommended to use a ÷2 divider for feedback.
3. In PLL bypass mode, the MPC9352 divides the input reference clock.
50.0
33.3
25.0
16.67
100.0
66.6
50.0
33.3
250.0
MHz
MHz
MHz
MHz
MHz
f
VCO
VCO lock frequency range
(4)
4. The input frequency f
ref
on CCLK must match the VCO frequency range divided by the feedback divider ratio FB: f
ref
= f
VCO
÷ FB.
200 400 MHz
f
MAX
Output Frequency ÷2 output
(5)
÷4 output
÷6 output
÷8 output
÷12 output
5. See Table 9 and Table 10 for output divider configurations.
100
50
33.3
25
16.67
200
100
66.6
50
33.3
MHz
MHz
MHz
MHz
MHz
f
refDC
Reference Input Duty Cycle 25 75 %
t
r
, t
f
CCLK Input Rise/Fall Time 1.0 ns 0.8 to 2.0 V
t
(∅)
Propagation Delay CCLK to FB_IN f
ref
> 40 MHz
(static phase offset) f
ref
< 40 MHz
–50
–200
+150
+150
ps
ps
PLL locked
t
sk(O)
Output-to-output Skew
(6)
all outputs, any frequency
within QA output bank
within QB output bank
within QC output bank
6. See application section for part-to-part skew calculation.
200
200
100
100
ps
ps
ps
ps
DC Output duty cycle 47 50 53 %
t
r
, t
f
Output Rise/Fall Time 0.1 1.0 ns 0.6 to 1.8 V
t
PLZ, HZ
Output Disable Time 8 ns
t
PZL, ZH
Output Enable Time 10 ns
t
JIT(CC)
Cycle-to-cycle jitter
output frequencies mixed RMS (1 σ)
outputs are in any ÷4 and ÷6 combination RMS (1 σ)
all outputs same frequency RMS (1 σ)
400
250
100
ps
ps
ps
t
JIT(PER)
Period Jitter output frequencies mixed RMS (1 σ)
outputs are in any ÷4 and ÷6 combination RMS (1 σ)
all outputs same frequency RMS (1 σ)
200
150
75
ps
ps
ps
t
JIT(∅)
I/O Phase Jitter ÷4 feedback divider RMS (1 σ)
(7)
÷6 feedback divider RMS (1 σ)
÷8 feedback divider RMS (1 σ)
÷12 feedback divider RMS (1 σ)
7. See application section for a jitter calculation for other confidence factors than 1 σ.
15
20
18 – 20
25
ps
ps
ps
ps
BW PLL closed loop bandwidth
(8)
÷4 feedback
÷6 feedback
÷8 feedback
÷12 feedback
8. –3 dB point of PLL transfer characteristics.
1.0 – 8.0
0.7 – 3.0
0.5 – 2.5
0.4 – 1.0
MHz
MHz
MHz
MHz
t
LOCK
Maximum PLL Lock Time 10 ms
Advanced Clock Drivers Devices
8 Freescale Semiconductor
MPC9352
APPLICATIONS INFORMATION
Programming the MPC9352
The MPC9352 supports output clock frequencies from
16.67 to 200 MHz. Different feedback and output divider
configurations can be used to achieve the desired input to
output frequency relationship. The feedback frequency and
divider should be used to situate the VCO in the frequency
lock range between 200 and 400 MHz for stable and optimal
operation. The FSELA, FSELB, FSELC pins select the
desired output clock frequencies. Possible frequency ratios
of the reference clock input to the outputs are 1:1, 1:2, 1:3,
3:2 as well as 2:3, 3:1 and 2:1. Tabl e 9 and Table 1 0
illustrates the various output configurations and frequency
ratios supported by the MPC9352. See also Figure 3 to
Figure 6 for further reference. A
÷2 output divider cannot be
used for feedback.
Table 9. MPC9352 Example Configuration (F_RANGE = 0)
PLL
Feedback
fref
(1)
[MHz]
1. fref is the input clock reference frequency (CCLK).
FSELA FSELB FSELC QA[0:4]:fref ratio QB[0:3]:fref ratio QC[0:1]:fref ratio
VCO ÷ 4
(2)
2. QAx connected to FB_IN and FSELA=0.
50-100 0 0 0 fref (50-100 MHz) fref (50-100 MHz) fref * 2 (100-200 MHz)
0 0 1 fref (50-100 MHz) fref (50-100 MHz) fref (50-100 MHz)
1 0 0 fref * 2÷3 (33-66 MHz) fref (50-100 MHz) fref * 2 (100-200 MHz)
1 0 1 fref * 2÷3 (33-66 MHz) fref (50-100 MHz) fref (50-100 MHz)
VCO ÷ 6
(3)
3. QAx connected to FB_IN and FSELA=1.
33.3-66.67 1 0 0 fref (33-66 MHz) fref * 3÷2 (50-100 MHz) fref * 3 (100-200 MHz)
1 0 1 fref (33-66 MHz) fref * 3÷2 (50-100 MHz) fref * 3÷2 (50-100 MHz)
1 1 0 fref (33-66 MHz) fref * 3 (100-200 MHz) fref * 3 (100-200 MHz)
1 1 1 fref (33-66 MHz) fref * 3 (100-200 MHz) fref * 3÷2 (50-100 MHz)
Table 10. MPC9352 Example Configurations (F_RANGE = 1)
PLL Feedback
fref
(1)
[MHz]
1. fref is the input clock reference frequency (CCLK).
FSELA FSELB FSELC QA[0:4]:fref ratio QB[0:3]:fref ratio QC[0:1]:fref ratio
VCO ÷ 8
(2)
2. QAx connected to FB_IN and FSELA=0.
25-50 0 0 0 fref (25-50 MHz) fref (25-50 MHz) fref * 2 (50-100 MHz)
0 0 1 fref (25-50 MHz) fref (25-50 MHz) fref (25-50 MHz)
1 0 0 fref * 2÷3 (16-33 MHz) fref (25-50 MHz) fref * 2 (50-100 MHz)
1 0 1 fref * 2÷3 (16-33 MHz) fref (25-50 MHz) fref (25-50 MHz)
VCO ÷ 12
(3)
3. QAx connected to FB_IN and FSELA=1.
16.67-33.3 1 0 0 fref (16-33 MHz) fref * 3÷2 (25-50 MHz) fref * 3 (50-100 MHz)
1 0 1 fref (16-33 MHz) fref * 3÷2 (25-50 MHz) fref * 3÷2 (25-50 MHz)
1 1 0 fref (16-33 MHz) fref * 3 (50-100 MHz) fref * 3 (50-100 MHz)
1 1 1 fref (16-33 MHz) fref * 3 (50-100 MHz) fref * 3÷2 (25-50 MHz)
Advanced Clock Drivers Devices
Freescale Semiconductor 9
MPC9352
Example Configurations for the MPC9352
MPC9352 configuration to multiply the reference
frequency by 3, 3 ÷ 2 and 1. PLL feedback of
QA4 = 33.3 MHz.
Figure 4. MPC9352 Zero Delay Buffer Configuration
Figure 5. MPC9352 Default Configuration Figure 6. MPC9352 Zero Delay Buffer
Configuration 2
MPC9352
fref = 100 MHz
100 MHz
100 MHz
100 MHz (Feedback)
QA0
QA1
QA2
QA3
QA4
QB0
QB1
QB2
QB3
QC0
QC1
CCLK
FB_IN
FSELA
FSELB
FSELD
F_RANGE
200 MHz
MPC9352 default configuration (feedback of QB0 = 100 MHz).
All control pins are left open.
MPC9352
fref = 62.5 MHz
62.5 MHz
62.5 MHz
62.5 MHz (Feedback)
QA0
QA1
QA2
QA3
QA4
QB0
QB1
QB2
QB3
QC0
QC1
CCLK
FB_IN
FSELA
FSELB
FSELC
F_RANGE
62.5 MHz
MPC9352 zero-delay (feedback of QB0 = 62.5 MHz). All
control pins are left open except FSELC = 1. All outputs
are locked in frequency and phase to the input clock.
MPC9352
fref = 33.3 MHz
33.3 MHz
50 MHz
33.3 MHz (Feedback)
QA0
QA1
QA2
QA3
QA4
QB0
QB1
QB2
QB3
QC0
QC1
CCLK
FB_IN
FSELA
FSELB
FSELC
F_RANGE
100 MHz
MPC9352
fref = 33.3 MHz
33.3 MHz
33.3 MHz
33.3 MHz (Feedback)
QA0
QA1
QA2
QA3
QQ4
QB0
QB1
QB2
QB3
QC0
QC1
CCLK
FB_IN
FSELA
FSELB
FSELC
F_RANGE
33.3 MHz
MPC9352 zero-delay (feedback of QB0 = 33.3 MHz).
Equivalent to Table 2 except F_RANGE = 1 enabling a
lower input and output clock frequency.
Frequency Range Min Max
Input 50 MHz 100 MHz
QA outputs 50 MHz 10 MHz
QB outputs 50 MHz 100 MHz
QC outputs 100 MHz 200 MHz
Frequency Range Min Max
Input 50 MHz 100 MHz
QA outputs 50 MHz 10 MHz
QB outputs 50 MHz 100 MHz
QC outputs 50 MHz 100 MHz
Frequency Range
Min Max
Input 25 MHz 50 MHz
QA outputs 50 MHz 10 MHz
QB outputs 50 MHz 100 MHz
QC outputs 100 MHz 200 MHz
Frequency Range Min Max
Input 25 MHz 50 MHz
QA outputs 25 MHz 50 MHz
QB outputs 25 MHz 50 MHz
QC outputs 25 MHz 50 MHz
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
Figure 3. MPC9352 Default Configuration
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16

MPC9352FA

Mfr. #:
Buy MPC9352FA
Manufacturer:
NXP Semiconductors
Description:
IC CLOCK CMOS LV 1:11 32-LQFP
Lifecycle:
New from this manufacturer.
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