2010-2015 Microchip Technology Inc. DS30009622M-page 41
PIC18F2XXX/4XXX FAMILY
TABLE 5-3: PIC18F2XXX/4XXX FAMILY BIT DESCRIPTIONS
Bit Name
Configuration
Words
Description
IESO CONFIG1H Internal External Switchover bit
1 = Internal External Switchover mode is enabled
0 = Internal External Switchover mode is disabled
FCMEN CONFIG1H Fail-Safe Clock Monitor Enable bit
1 = Fail-Safe Clock Monitor is enabled
0 = Fail-Safe Clock Monitor is disabled
FOSC<3:0> CONFIG1H Oscillator Selection bits
11xx = External RC oscillator, CLKO function on RA6
101x = External RC oscillator, CLKO function on RA6
1001 = Internal RC oscillator, CLKO function on RA6, port function on RA7
1000 = Internal RC oscillator, port function on RA6, port function on RA7
0111 = External RC oscillator, port function on RA6
0110 = HS oscillator, PLL is enabled (Clock Frequency = 4 x FOSC1)
0101 = EC oscillator, port function on RA6
0100 = EC oscillator, CLKO function on RA6
0011 = External RC oscillator, CLKO function on RA6
0010 = HS oscillator
0001 = XT oscillator
0000 = LP oscillator
FOSC<3:0> CONFIG1H Oscillator Selection bits
(PIC18F2455/2550/4455/4550, PIC18F2458/2553/4458/4553 and
PIC18F2450/4450 devices only)
111x = HS oscillator, PLL is enabled, HS is used by USB
110x = HS oscillator, HS is used by USB
1011 = Internal oscillator, HS is used by USB
1010 = Internal oscillator, XT is used by USB
1001 = Internal oscillator, CLKO function on RA6, EC is used by USB
1000 = Internal oscillator, port function on RA6, EC is used by USB
0111 = EC oscillator, PLL is enabled, CLKO function on RA6, EC is used by USB
0110 = EC oscillator, PLL is enabled, port function on RA6, EC is used by USB
0101 = EC oscillator, CLKO function on RA6, EC is used by USB
0100 = EC oscillator, port function on RA6, EC is used by USB
001x = XT oscillator, PLL is enabled, XT is used by USB
000x = XT oscillator, XT is used by USB
USBDIV CONFIG1L USB Clock Selection bit
(PIC18F2455/2550/4455/4550, PIC18F2458/2553/4458/4553 and
PIC18F2450/4450 devices only)
Selects the clock source for full-speed USB operation:
1 = USB clock source comes from the 96 MHz PLL divided by 2
0 = USB clock source comes directly from the OSC1/OSC2 oscillator block;
no divide
CPUDIV<1:0> CONFIG1L CPU System Clock Selection bits
(PIC18F2455/2550/4455/4550, PIC18F2458/2553/4458/4553 and
PIC18F2450/4450 devices only)
11 = CPU system clock divided by 4
10 = CPU system clock divided by 3
01 = CPU system clock divided by 2
00 = No CPU system clock divide
Note 1: The BBSIZ bits, BBSIZ<1:0> and BBSIZ<2:1> bits, cannot be changed once any of the following
code-protect bits are enabled: CPB or CP0, WRTB or WRT0, EBTRB or EBTR0.
2: Not available in PIC18FXX8X and PIC18F2450/4450 devices.