Philips Semiconductors Product specification
74LV377
Octal D-type flip-flop with data enable;
positive edge-trigger
1998 Jun 10
7
AC WAVEFORMS
V
M
= 1.5V at V
CC
2.7V
V
M
= 0.5V * V
CC
at V
CC
2.7V
V
OL
and V
OH
are the typical output voltage drop that occur with the
output load.
SV00707
V
M
CP INPUT
V
OL
GND
V
OH
V
CC
Q
n
OUTPUT
V
M
t
PLH
t
PHL
t
W
1/f
max
Figure 1. Clock (CP) to output (Q
n
) propagation delays,
the clock pulse width and the maximum clock pulse frequency.
V
M
E INPUT
CP INPUT
D
n
INPUT
GND
GND
GND
STABLE
V
CC
V
CC
V
CC
V
M
V
M
t
su
t
su
tW
t
h
t
h
t
h
t
su
SV00671
NOTE: The shaded areas indicate when the input is permitted
to change for predictable output performance.
Figure 2. Data set-up and hold times from the data input (Dn)
and from the enable input (E
) to the clock (CP).
TEST CIRCUIT
PULSE
GENERATOR
R
T
V
I
D.U.T.
V
O
C
L
R
L
= 1k
V
CC
Test Circuit for switching times
DEFINITIONS
V
CC
V
I
< 2.7V V
CC
TEST
t
PLH/
t
PHL
R
T
= Termination resistance should be equal to Z
OUT
of pulse generators.
50pF
SV00901
R
L
= Load resistor
C
L
= Load capacitance includes jig and probe capacitance
2.7–3.6V 2.7V
Figure 3. Load circuitry for switching times
