EN5336QI
10 www.altera.com/enpirion
of V
OUT
and below the user programmed OVP
trip-point. If the output voltage goes outside of
this range, the POK signal will be a logic low until
the output voltage has returned to within this
range. In the event of an over-voltage condition
the POK signal will go low and will remain in this
condition until the output voltage has dropped to
95% of the programmed output voltage before
returning to the high state.
NOTE: If no over voltage protection is used, POK
will remain “highas long as V
OUT
remains above
90% of the nominal V
OUT
setting.
Over-Current Protection
The current limit function is achieved by sensing
the current flowing through the sense P-
MOSFET. When the sensed current exceeds the
current limit, both NFET and PFET switches are
turned off. If the over-current condition is
removed, the over-current protection circuit will
enable the PWM operation. This circuit is
designed to provide high noise immunity.
The nominal over current trip point is set to 4.5A.
It is possible to increase the over-current set
point by about 50% by connecting a 7.5k
resistor between ROCP (pin 27) and GND. The
typical voltage at the ROCP pin is 0.75V.
In some cases, such as the start-up of FPGA
devices, it is desirable to blank the over-current
protection feature. In order to disable over-
current protection, the ROCP pin should be tied
to any voltage between 2.5V and PVIN.
Over-Voltage Protection
When the output voltage exceeds 120% of the
programmed output voltage, the PWM operation
stops, the lower N-MOSFET is turned on and the
POK signal goes low. When the output voltage
drops below 95% of the programmed output
voltage, normal PWM operation resumes and
POK returns to its high state.
Thermal Overload Protection
Thermal shutdown will disable operation once
the Junction temperature exceeds approximately
150ºC. Once the junction temperature drops by
approx 25ºC, the converter will re-start with a
normal soft-start.
Input Under-voltage Lock-out
Circuitry is provided to ensure that when the
input voltage is below the specified voltage
range, the converter will not start-up. Circuits for
hysteresis, input de-glitch and output leading
edge blanking are included to ensure high noise
immunity and prevent false tripping.
Compensation
The EN5336QI is internally compensated
through the use of a type 3 compensation
network and is optimized for use with about 50uF
of output capacitance and will provide excellent
loop bandwidth and transient performance for
most applications. (See the section on Capacitor
Selection for details on recommended capacitor
types.) Voltage mode operation provides high
noise immunity at light load.
In some cases modifications to the compensation
may be required. For more information, contact
Power Applications support.
EN5336QI
11 www.altera.com/enpirion
Layout Recommendation
Figure 4 shows critical components and layer 1
traces of a recommended minimum footprint
EN5336QI layout. Alternate ENABLE
configurations and other small signal pins need
to be connected and routed according to specific
customer application. Please see the Gerber files
on the Altera website www.altera.com/enpirion
for exact dimensions and other layers. Please
refer to Figure 4 while reading the layout
recommendations in this section.
Recommendation 1: Input and output filter
capacitors should be placed on the same side of
the PCB, and as close to the EN5336QI package
as possible. They should be connected to the
device with very short and wide traces. Do not
use thermal reliefs or spokes when connecting
the capacitor pads to the respective nodes. The
+V and GND traces between the capacitors and
the EN5336QI should be as close to each other
as possible so that the gap between the two
nodes is minimized, even under the capacitors.
Recommendation 2: Two PGND pins are
dedicated to the input circuit, and two to the
output circuit. The slit in Figure 4 separating the
input and output GND circuits helps minimize
noise coupling between the converter input and
output switching loops.
Recommendation 3: The system ground plane
should be the first layer immediately below the
surface layer. This ground plane should be
continuous and un-interrupted below the
converter and the input/output capacitors. Please
see the Gerber files on the Altera website
www.altera.com/enpirion.
Recommendation 4: The large thermal pad
underneath the component must be connected to
the system ground plane through as many vias
as possible.
Figure 4: Top PCB Layer Critical Components
and Copper for Minimum Footprint
The drill diameter of the vias should be 0.33mm,
and the vias must have at least 1 oz. copper
plating on the inside wall, making the finished
hole size around 0.20-0.26mm. Do not use
thermal reliefs or spokes to connect the vias to
the ground plane. This connection provides the
path for heat dissipation from the converter.
Please see Figures: 7, 8, and 9.
Recommendation 5: Multiple small vias (the
same size as the thermal vias discussed in
recommendation 4 should be used to connect
ground terminal of the input capacitor and output
capacitors to the system ground plane. It is
preferred to put these vias under the capacitors
along the edge of the GND copper closest to the
+V copper. Please see Figure 4. These vias
connect the input/output filter capacitors to the
GND plane, and help reduce parasitic
inductances in the input and output current loops.
If the vias cannot be placed under C
IN
and C
OUT
,
then put them just outside the capacitors along
the GND slit separating the two components. Do
not use thermal reliefs or spokes to connect
these vias to the ground plane.
Recommendation 6: AVIN is the power supply
for the internal small-signal control circuits. It
should be connected to the input voltage at a
EN5336QI
12 www.altera.com/enpirion
quiet point. In Figure 4 this connection is made at
the input capacitor close to the V
IN
connection.
Recommendation 7: The layer 1 metal under
the device must not be more than shown in
Figure 4. See the section regarding exposed
metal on bottom of package. As with any switch-
mode DC/DC converter, try not to run sensitive
signal or control lines underneath the converter
package on other layers.
Recommendation 8: The external feedback
resistor sense point (top feedback resistor)
should be just after the last output filter capacitor.
Keep the sense trace as short as possible in
order to avoid noise coupling into the control
loop. Place the feedback resistor components
near the XFB pin. The ground for the external
feedback resistor should be connected to a quiet
ground such as AGND.

EN5336QI

Mfr. #:
Manufacturer:
Intel / Altera
Description:
Switching Voltage Regulators 3AMP BUCK CONVERTER
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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