EMIF10-LCD01C2

®
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EMIF10-LCD01C2
10 LINE EMI FILTER
AND ESD PROTECTION
REV. 1
Lead free coated Flip-Chip
(25 bumps)
August 2005
MAIN PRODUCT CHARACTERISTICS:
Where EMI filtering in ESD sensitive equipment is
required :
LCD for Mobile phones
Computers and printers
Communication systems
MCU Boards
DESCRIPTION
The EMIF10-LCD01C2 is a 10 line highly integrat-
ed devices designed to suppress EMI/RFI noise in
all systems subjected to electromagnetic interfer-
ences. The EMIF10 flip chip packaging means the
package size is equal to the die size.
This filter includes an ESD protection circuitry,
which prevents the device from destruction when
subjected to ESD surges up 15kV.
BENEFITS
EMI symmetrical (I/O) low-pass filter
High efficiency in EMI filtering
Very low PCB space consuming: < 7mm
2
Coating resin on back side
Very thin package: 0.69 mm
High efficiency in ESD suppression on input
pins (IEC61000-4-2 level 4)
High reliability offered by monolithic integration
High reducing of parasitic elements through
integration and wafer level packaging.
Lead free package
COMPLIES WITH THE FOLLOWING STANDARDS:
IEC61000-4-2:
Level 4 input pins 15kV (air discharge)
8kV (contact discharge)
Level 1 output pins 2kV (air discharge)
2kV (contact discharge)
MIL STD 833E - Method 3015-6 Class 3
Table 1: Order Code
Part Number Marking
EMIF10-LCD01C2 FL
IPAD™
Figure 1: Pin Configuration (bump side)
A
B
C
D
E
12
3
4
5
O10 O8 O6
O4 O2
O9 O7
O5 O3 O1
I10 I8 I6
I4 I2
I9
GNDGND GND
I5
I1
I7
GNDGND
I3
Figure 2: Basic Cell Configuration
Input
GND GND GND
Output
Low-pass Filter
Ri/o = 100
Cline = 35pF
EMIF10-LCD01C2
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Table 2: Absolute Maximum Ratings (T
amb
= 25°C)
Table 3: Electrical Characteristics (T
amb
= 25°C)
Symbol Parameter Value Unit
T
j
Junction temperature 125 °C
T
op
Operating temperature range
-40 to + 85
°C
T
stg
Storage temperature range -55 to +150 °C
Symbol Parameter
V
BR
Breakdown voltage
I
RM
Leakage current @ V
RM
V
RM
Stand-off voltage
V
CL
Clamping voltage
Rd Dynamic resistance
I
PP
Peak pulse current
R
I/O
Series resistance between Input & Output
Cline Input capacitance per line
Symbol Test conditions Min. Typ. Max. Unit
V
BR
I
R
= 1 mA
6810V
I
RM
V
RM
= 3V
500 nA
R
I/O
90 100 110
Cline
@ 0V bias 28 35 pF
Rt / Ft Induced rise and fall time 10-90% at 26 MHz fre-
quency signal V = 1.9 V (Rt / Ft input 1 ns, 50
impedance generator)
8
(1)
ns
(1) guaranteed by design
Figure 3: S21(dB) all lines attenuation
measurement and Aplac simulation
Figure 4: Analog cross talk measurements
I
V
I
F
I
RM
I
R
I
PP
V
RM
V
F
V
BR
V
CL
EMIF10-LCD01C2
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Figure 5: ESD response to IEC61000-4-2
(+15kV air discharge) on one input and on one
output
Figure 6: ESD response to IEC61000-4-2 (-15kV
air discharge) on one input and on one output
Figure 7: Line capacitance versus applied
voltage
Figure 8: Rise time 10-90% measurements with
1.9V signal at 26 MHz frequency (50
generator)
Figure 9: Fall time 10-90% measurements with
1.9V signal at 26 MHz frequency (50
generator)
V
in
V
out
0
5
10
15
20
25
30
35
0.0 1.0 2.0 3.0 4.0 5.0
VLine(V)
CLine(pF)

EMIF10-LCD01C2

Mfr. #:
Manufacturer:
STMicroelectronics
Description:
EMI Filter Circuits unidirect 10line flt 47pF -25db @ 900MHz
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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