LTC6412
15
6412fa
APPLICATIONS INFORMATION
Introduction
The LTC6412 is a high linearity, fully-differential analog-
controlled variable-gain amplifi er (VGA) optimized for
application frequencies in the range of 1MHz to 500MHz.
The VGA architecture provides a constant OIP3 and constant
output noise level (NF + Gain) over the 31dB gain-control
range and thus exhibits a uniform spurious-free dynamic
range (SFDR) over gain. This constant SFDR characteristic
is ideal for use in receiver IF chains that are upstream from
a signal sink such as a demodulator or ADC.
The low supply voltage requirements and fully differential
design are compatible with many other LTC mixer, amplifi er
and ADC products for use in compact, low voltage, fully
differential receiver chains. For non-differential systems,
the 50Ω input impedance and 200Ω output impedance
are easily converted to single-ended 50Ω ports with
inexpensive 1:1 and 4:1 baluns.
Gain Characteristics
The LTC6412 provides a continuously adjustable gain range
of –14dB to 17dB that is linear-in-dB with respect to the
control voltages applied to +V
G
and –V
G
. These control
pins can be operated with a differential signal, but it is more
common to operate one of the V
G
pins with a single-ended
control signal while connecting the other V
G
pin to the
provided V
REF
pin. In this way, either a positive gain-control
slope or negative gain-control slope is easily achieved:
Negative Gain-Control Slope. Tie +V
G
to V
REF
and apply
gain control voltage to the –V
G
pin. Gain decreases with
increasing –V
G
voltage.
Positive Gain-Control Slope. Tie –V
G
to V
REF
and apply
gain control voltage to the +V
G
pin. Gain increases with
increasing +V
G
voltage.
When connected in this typical single-ended confi guration,
the active control input range extends from 0.1V to 1.1V.
This control input range can be extended using a resistor
divider with a suitably low output resistance. For example,
two series resistors of 1k each would extend the control
input range from 0.2V to 2.2V while providing an effective
500Ω Thevinin equivalent source resistance, a relatively
small loading effect compared to the 10k input resistance
of the +V
G
/–V
G
terminals.
Port Characteristics
The LTC6412 provides a nominal 50Ω differential input
impedance and 200Ω differential output impedance over
the operating frequency range.
The input impedance characteristic derives from the
differential attenuator ladder shown in the Block Diagram.
The internal circuit controls the RF connections to this
attenuator ladder and generates the appropriate common
mode DC voltage to this port. The differential attenuator
ladder creates a virtual ground node that needs a capacitor
bypass to ground at the V
CM
pin to effectively attenuate
any common mode signal presented to the input port.
The +V
IN
and –V
IN
pins are connected to the input signal
through DC blocking capacitors as shown in Test Circuit A
and Test Circuit B, Figures 1-4.
The output impedance characteristic derives from the open-
collector equivalent circuit shown in Figure 7. The action of
the differential shunt, lowpass fi lter, and internal feedback
presents an effective differential output impedance of
200Ω to 300Ω between the +OUT and –OUT pins over the
operating band. The +V
OUT
and –V
OUT
pins are connected
to the output port using shunt inductors or a transformer
to provide a DC path to the supply voltage. The DC block
to the circuit output is usually accomplished using series
capacitors. These blocking capacitors can be avoided if a
fl ux transformer is used at the output. Figure 9 illustrates
a few common inductor and balun transformer methods
for coupling the AC signal and DC supply to the output
pins. This is discussed further in the Typical Application
Circuits section.
Power Supplies
Inductance to the supply path can degrade the performance
of the LTC6412. It is recommended that low inductance
bypass capacitors are installed very close to each of
the V
CC
pins. 1000pF and 0.1μF parallel capacitors are
recommended with the smaller capacitor placed closer to
the V
CC
pin. Do not leave any supply pins disconnected. For
best performance, DC bias voltage to the +OUT and –OUT
pins must be within 100mV of V
CC
. The Exposed Pad on
the underside of the package must be connected to ground
with low inductance and low thermal resistance. Refer to
details of DC1464A (Test Circuit A) for an example of proper
