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LTC1483CN8#PBF

P1-P3P4-P6P7-P8
4
LTC1483
sn1483 1483fs
TYPICAL PERFORMANCE CHARACTERISTICS
UW
Driver Differential Output Voltage
vs Temperature
TEMPERATURE (°C)
–50
DIFFERENTIAL VOLTAGE (V)
2.5
2.4
2.3
2.2
2.1
2.0
1.9
1.8
1.7
1.6
1.5
0
50
75
1483 G04
–25
25
100
125
R
L
= 54Ω
Driver Output High Voltage
vs Output Current
OUTPUT VOLTAGE (V)
0
OUTPUT CURRENT (mA)
2
4
5
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
1483 G06
13
T
A
= 25°C
PIN FUNCTIONS
UUU
DI (Pin 4): Driver Input. If the driver outputs are enabled
(DE high) then a low on DI forces the outputs A low and B
high. A high on DI with the driver outputs enabled will force
A high and B low.
GND (Pin 5): Ground.
A (Pin 6): Driver Output/Receiver Input.
B (Pin 7): Driver Output/Receiver Input.
V
CC
(Pin 8): Positive Supply. 4.75V < V
CC
< 5.25V.
RO (Pin 1): Receiver Output. If the receiver output is
enabled (RE low), then if A > B by 200mV, RO will be high.
If A < B by 200mV, then RO will be low.
RE (Pin 2): Receiver Output Enable. A low enables the
receiver output, RO. A high input forces the receiver
output into a high impedance state.
DE (Pin 3): Driver Outputs Enable. A high on DE enables
the driver output. A, B and the chip will function as a line
driver. A low input will force the driver outputs into a high
impedance state and the chip will function as a line
receiver. If RE is high and DE is low, the part will enter a low
power (1µA) shutdown state.
FU CTIO TABLES
UU
LTC1483 Transmitting
INPUTS OUTPUTS
RE DE DI B A
X1101
X1010
00XZZ
1 0 X Z* Z*
*Shutdown mode for LTC1483
LTC1483 Receiving
INPUTS OUTPUTS
RE DE A – B RO
00≥0.2V 1
00≤–0.2V 0
0 0 Inputs Open 1
10 X Z*
*Shutdown mode for LTC1483
OUTPUT VOLTAGE
0
70
60
50
40
30
20
10
0
3
1483 G05
12 4
OUTPUT CURRENT (mA)
T
A
= 25°C
Driver Output Low Voltage
vs Output Current
5
LTC1483
sn1483 1483fs
TEST CIRCUITS
SWITCHI G TI E WAVEFOR S
UW W
3V
DE
A
B
DI
R
DIFF
C
L1
C
L2
RO
15pF
A
B
RE
LTC1483 • F03
Figure 3. Driver/Receiver Timing Test Circuit Figure 4. Driver Timing Test Load
OUTPUT
UNDER TEST
C
L
S1
S2
V
CC
500Ω
LTC1483 • F04
V
OD
A
B
R
R
V
OC
LTC1483 • F01
RECEIVER
OUTPUT
C
RL
1k
S1
S2
TEST POINT
V
CC
1k
LTC1483 • F02
Figure 1. Driver DC Test Load Figure 2. Receiver Timing Test Load
Figure 6. Driver Enable and Disable Times
1.5V
2.3V
2.3V
t
ZH(SHDN)
,
t
ZH
t
ZL(SHDN)
,
t
ZL
1.5V
t
LZ
0.5V
0.5V
t
HZ
OUTPUT NORMALLY LOW
OUTPUT NORMALLY HIGH
3V
0V
DE
5V
V
OL
V
OH
0V
A, B
A, B
LTC1483 • F06
t
r
≤ 10ns, t
f
≤ 10ns
Figure 5. Driver Propagation Delays
DI
3V
1.5V
t
PLH
t
r
t
SKEW
1/2 V
O
V
O
t
r
≤ 10ns, t
f
≤ 10ns
90%
10%
0V
B
A
V
O
–V
O
0V
90%
1.5V
t
PHL
t
SKEW
1/2 V
O
10%
t
f
V
DIFF
= V(A) – V(B)
LTC1483 • F05
6
LTC1483
sn1483 1483fs
SWITCHI G TI E WAVEFOR S
UW W
1.5V
t
PHL
RO
–V
OD2
A – B
0V 0V
1.5V
t
PLH
OUTPUT
INPUT
V
OD2
V
OL
V
OH
LTC1483 • F07
t
r
≤ 10ns, t
f
≤ 10ns
Figure 7. Receiver Propagation Delays
1.5V
t
ZL(SHDN)
, t
ZL
t
ZH(SHDN)
, t
ZH
1.5V
1.5V
1.5V
t
LZ
0.5V
0.5V
t
HZ
OUTPUT NORMALLY LOW
OUTPUT NORMALLY HIGH
3V
0V
RE
5V
0V
RO
RO
LTC1483 • F08
t
r
≤ 10ns, t
f
≤ 10ns
Figure 8. Receiver Enable and Disable Times
APPLICATIO S I FOR ATIO
UU W U
Basic Theory of Operation
Traditionally RS485 transceivers have been designed us-
ing bipolar technology because the common-mode range
of the device must extend beyond the supplies and the
device must be immune to ESD damage and latch-up.
Unfortunately, most bipolar devices draw a large amount
of supply current, which is unacceptable for the numerous
applications that require low power consumption. The
LTC1483 is a CMOS RS485/RS422 transceiver which
features ultra-low power consumption without sacrificing
ESD and latch-up immunity.
The LTC1483 uses a proprietary driver output stage,
which allows a common-mode range that extends beyond
the power supplies while virtually eliminating latch-up and
providing excellent ESD protection. Figure 9 shows the
LTC1483 output stage while Figure 10 shows a conven-
tional CMOS output stage.
When the conventional CMOS output stage of Figure 10
enters a high impedance state, both the P-channel (P1)
and the N-channel (N1) are turned off. If the output is then
driven above V
CC
or below ground, the P+/N-well diode
(D1) or the N+/P-substrate diode (D2) respectively will
turn on and clamp the output to the supply. Thus, the
output stage is no longer in a high impedance state and is
not able to meet the RS485 common-mode range require-
ment. In addition, the large amount of current flowing
through either diode will induce the well-known CMOS
latch-up condition, which could destroy the device.
LOGIC
V
CC
SD3
P1
D1
OUTPUT
SD4
D2
N1
LTC1483 • F09
Figure 9. LTC1483 Output Stage
LOGIC
V
CC
P1
D1
OUTPUT
D2
N1
LTC1483 • F10
Figure 10. Conventional
CMOS Output Stage
P1-P3P4-P6P7-P8

LTC1483CN8#PBF

Mfr. #:
Buy LTC1483CN8#PBF
Manufacturer:
Analog Devices Inc.
Description:
RS-485 Interface IC Ultra-L Pwr RS485 L EMI Tran w/ SD
Lifecycle:
New from this manufacturer.
Delivery:
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