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NLV74VHC00DTR2G

P1-P3P4-P6
© Semiconductor Components Industries, LLC, 2014
September, 2014 − Rev. 7
1 Publication Order Number:
MC74VHC00/D
MC74VHC00
Quad 2-Input NAND Gate
The MC74VHC00 is an advanced high speed CMOS 2−input
NAND gate fabricated with silicon gate CMOS technology. It
achieves high speed operation similar to equivalent Bipolar Schottky
TTL while maintaining CMOS low power dissipation.
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output. The
inputs tolerate voltages up to 7 V, allowing the interface of 5 V
systems to 3 V systems.
Features
• High Speed: t
PD
= 3.7 ns (Typ) at V
CC
= 5 V
• Low Power Dissipation: I
CC
= 2 mA (Max) at T
A
= 25°C
• High Noise Immunity: V
NIH
= V
NIL
= 28% V
CC
• Power Down Protection Provided on Inputs
• Balanced Propagation Delays
• Designed for 2 V to 5.5 V Operating Range
• Low Noise: V
OLP
= 0.8 V (Max)
• Pin and Function Compatible with Other Standard Logic Families
• Latchup Performance Exceeds 300 mA
• ESD Performance: HBM > 2000 V; Machine Model > 200 V
• Chip Complexity: 32 FETs or 8 Equivalent Gates
• These Devices are Pb−Free and are RoHS Compliant
Figure 1. Pinout: 14−Lead Packages
(Top View)
1314 12 11 10 9 8
21 34567
V
CC
B4 A4 Y4 B3 A3 Y3
A1 B1 Y1 A2 B2 Y2 GND
L
L
H
H
L
H
L
H
FUNCTION TABLE
Inputs Output
AB
H
H
H
L
Y
A = Assembly Location
L, WL = Wafer Lot
Y = Year
W, WW = Work Week
G, G = Pb−Free Device
MARKING
DIAGRAMS
SO−14
D SUFFIX
CASE 751A
TSSOP−14
DT SUFFIX
CASE 948G
http://onsemi.com
VHC00G
AWLYWW
1
14
VHC
00
ALYW G
G
1
14
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
ORDERING INFORMATION
MC74VHC00
http://onsemi.com
2
3
Y1
1
A1
Figure 2. Logic Diagram
2
B1
6
Y2
4
A2
5
B2
8
Y3
9
A3
10
B3
11
Y4
12
A4
13
B4
Y = AB
MAXIMUM RATINGS
Symbol Parameter Value Unit
V
CC
Positive DC Supply Voltage −0.5 to +7.0 V
V
IN
Digital Input Voltage −0.5 to +7.0 V
V
OUT
DC Output Voltage −0.5 to V
CC
+0.5 V
I
IK
Input Diode Current −20 mA
I
OK
Output Diode Current $20 mA
I
OUT
DC Output Current, per Pin $25 mA
I
CC
DC Supply Current, V
CC
and GND Pins $75 mA
P
D
Power Dissipation in Still Air SOIC Package
TSSOP
200
180
mW
T
STG
Storage Temperature Range −65 to +150 °C
V
ESD
ESD Withstand Voltage Human Body Model (Note 1)
Machine Model (Note 2)
Charged Device Model (Note 3)
>2000
>200
N/A
V
I
LATCH−UP
Latch−Up Performance Above V
CC
and Below GND at 125°C (Note 4) $300 mA
q
JA
Thermal Resistance, Junction to Ambient SOIC Package
TSSOP
143
164
°C/W
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Tested to EIA/JESD22−A114−A
2. Tested to EIA/JESD22−A115−A
3. Tested to JESD22−C101−A
4. Tested to EIA/JESD78
RECOMMENDED OPERATING CONDITIONS
Symbol Characteristics Min Max Unit
V
CC
DC Supply Voltage 2.0 5.5 V
V
IN
DC Input Voltage 0 5.5 V
V
OUT
DC Output Voltage 0 V
CC
V
T
A
Operating Temperature Range, All Package Types −55 125 °C
t
r
, t
f
Input Rise or Fall Time V
CC
= 3.3 V + 0.3 V
V
CC
= 5.0 V + 0.5 V
0
0
100
20
ns/V
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
MC74VHC00
http://onsemi.com
3
DC ELECTRICAL CHARACTERISTICS
Symbol Parameter Test Conditions
V
CC
V
T
A
= 25°C
T
A
= −40 to
85°C
T
A
= −55 to
+125°C
Unit
Min Typ Max Min Max Min Max
V
IH
High−Level Input
Voltage
2.0
3.0 to
5.5
1.50
V
CC
x
0.7
1.50
V
CC
x
0.7
1.50
V
CC
x
0.7
V
V
IL
Low−Level Input
Voltage
2.0
3.0 to
5.5
0.50
V
CC
x
0.3
0.50
V
CC
x
0.3
0.50
V
CC
x
0.3
V
V
OH
High−Level
Output Voltage
V
in
= V
IH
or V
IL
I
OH
= − 50 mA
2.0
3.0
4.5
1.9
2.9
4.4
2.0
3.0
4.5
1.9
2.9
4.4
1.9
2.9
4.4
V
V
in
= V
IH
or V
IL
I
OH
= − 4 mA
I
OH
= − 8 mA
3.0
4.5
2.58
3.94
2.48
3.80
2.40
3.70
V
OL
Low−Level
Output Voltage
V
in
= V
IH
or V
IL
I
OL
= 50 mA
2.0
3.0
4.5
0.0
0.0
0.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
in
= V
IH
or V
IL
I
OL
= 4 mA
I
OL
= 8 mA
3.0
4.5
0.36
0.36
0.44
0.44
0.55
0.55
I
in
Input Leakage
Current
V
in
= 5.5 V or GND 0 to 5.5 $0.1 $1.0 $2.0
mA
I
CC
Quiescent Supply
Current
V
in
= V
CC
or GND 5.5 2.0 20 40
mA
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
AC ELECTRICAL CHARACTERISTICS (Input t
r
= t
f
= 3.0 ns)
Symbol Parameter Test Conditions
T
A
= 25°C
T
A
= −40 to
85°C
T
A
= −55 to
+125°C
Unit
Min Typ Max Min Max Min Max
t
PLH
,
t
PHL
Propagation
Delay, A or B to Y
V
CC
= 3.3 ± 0.3 V C
L
= 15 pF
C
L
= 50 pF
5.5
8.0
7.9
11.4
1.0
1.0
9.5
13.0
1.0
1.0
10
14.5
ns
V
CC
= 5.0 ± 0.5 V C
L
= 15 pF
C
L
= 50 pF
3.7
5.2
5.5
7.5
1.0
1.0
6.5
8.5
1.0
1.0
7.0
9.5
C
in
Input
Capacitance
4.0 10 10 10 pF
C
PD
Power Dissipation Capacitance (Note 5)
Typical @ 25°C, V
CC
= 5.0 V
pF
19
5. C
PD
is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: I
CC(OPR
)
= C
PD
V
CC
f
in
+ I
CC
/4 (per gate). C
PD
is used to determine the
no−load dynamic power consumption; P
D
= C
PD
V
CC
2
f
in
+ I
CC
V
CC
.
NOISE CHARACTERISTICS (Input t
r
= t
f
= 3.0 ns, C
L
= 50 pF, V
CC
= 5.0 V, Measured in SOIC Package)
Symbol
Characteristic
T
A
= 25°C
Unit
Typ Max
V
OLP
Quiet Output Maximum Dynamic V
OL
0.3 0.8 V
V
OLV
Quiet Output Minimum Dynamic V
OL
− 0.3 − 0.8 V
V
IHD
Minimum High Level Dynamic Input Voltage 3.5 V
V
ILD
Maximum Low Level Dynamic Input Voltage 1.5 V
P1-P3P4-P6

NLV74VHC00DTR2G

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Manufacturer:
ON Semiconductor
Description:
Logic Gates LOG CMOS GATE NAND
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