6.42
IDT709389L
High-Speed 64K x 18 Synchronous Pipelined Dual-Port Static RAM Industrial and Commercial Temperature Ranges
14
4844 drw 19
IDT709389
CE
0
CE
1
CE
1
CE
0
CE
0
CE
1
16
CE
1
CE
0
V
CC
V
CC
IDT709389
IDT709389
IDT709389
Control Inputs
Control Inputs
Control Inputs
Control Inputs
CNT RS
CLK
AD S
CNT EN
R/W
UB, LB
OE
A Functional Description
The IDT709389 provides a true synchronous Dual-Port Static
RAM interface. Registered inputs provide minimal set-up and hold
times on address, data, and all critical control inputs. All internal
registers are clocked on the rising edge of the clock signal, however,
the self-timed internal write pulse is independent of the LOW to HIGH
transition of the clock signal.
An asynchronous output enable is provided to ease asynchronous
bus interfacing. Counter enable inputs are also provided to stall the
operation of the address counters for fast interleaved memory appli-
cations.
CE
0 = VIH or CE1 = VIL for one clock cycle will power down the
internal circuitry to reduce static power consumption. Multiple chip
enables allow easier banking of multiple IDT709389's for depth
expansion configurations. When the Pipelined output mode is en-
abled, two cycles are required with CE
0 = VIL and CE1 = VIH to re-
activate the outputs.
Depth and Width Expansion
The IDT709389 features dual chip enables (refer to Truth Table I)
in order to facilitate rapid and simple depth expansion with no
requirements for external logic. Figure 4 illustrates how to control the
various chip enables in order to expand two devices in depth.
The 709389 can also be used in applications requiring expanded
width, as indicated in Figure 4. Since the banks are allocated at the
discretion of the user, the external controller can be set up to drive the
input signals for the various devices as required to allow for 36-bit
or wider applications.
Figure 4. Depth and Width Expansion with IDT709389
