Stratix 10 GX/SX Device Overview
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S10-OVERVIEW | 2018.08.08
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Contents
1. Intel
®
Stratix
®
10 GX/SX Device Overview.................................................................... 3
1.1. Intel Stratix 10 Family Variants...............................................................................4
1.1.1. Available Options....................................................................................... 6
1.2. Innovations in Intel Stratix 10 FPGAs and SoCs......................................................... 6
1.3. FPGA and SoC Features Summary...........................................................................8
1.4. Intel Stratix 10 Block Diagram...............................................................................11
1.5. Intel Stratix 10 FPGA and SoC Family Plan..............................................................11
1.6. HyperFlex Core Architecture.................................................................................. 15
1.7. Heterogeneous 3D SiP Transceiver Tiles.................................................................. 16
1.8. Intel Stratix 10 Transceivers................................................................................. 17
1.8.1. PMA Features......................................................................................... 18
1.8.2. PCS Features..........................................................................................20
1.9. PCI Express Gen1/Gen2/Gen3 Hard IP...................................................................21
1.10. Interlaken PCS Hard IP...................................................................................... 21
1.11. 10G Ethernet Hard IP........................................................................................ 22
1.12. External Memory and General Purpose I/O........................................................... 22
1.13. Adaptive Logic Module (ALM).............................................................................. 23
1.14. Core Clocking................................................................................................... 24
1.15. Fractional Synthesis PLLs and I/O PLLs.................................................................25
1.16. Internal Embedded Memory................................................................................25
1.17. Variable Precision DSP Block............................................................................... 25
1.18. Hard Processor System (HPS)............................................................................. 28
1.18.1. Key Features of the Intel Stratix 10 HPS...................................................29
1.19. Power Management........................................................................................... 32
1.20. Device Configuration and Secure Device Manager (SDM)......................................... 32
1.21. Device Security..................................................................................................34
1.22. Configuration via Protocol Using PCI Express..........................................................34
1.23. Partial and Dynamic Reconfiguration.................................................................... 35
1.24. Fast Forward Compile......................................................................................... 35
1.25. Single Event Upset (SEU) Error Detection and Correction........................................35
1.26. Document Revision History for the Intel Stratix 10 GX/SX Device Overview................36
Contents
Stratix 10 GX/SX Device Overview
2
1. Intel
®
Stratix
®
10 GX/SX Device Overview
Intel’s 14-nm Intel
®
Stratix
®
10 GX FPGAs and SX SoCs deliver 2X the core
performance and up to 70% lower power over previous generation high-performance
FPGAs.
Featuring several groundbreaking innovations, including the all new HyperFlex
core
architecture, this device family enables you to meet the demand for ever-increasing
bandwidth and processing performance in your most advanced applications, while
meeting your power budget.
With an embedded hard processor system (HPS) based on a quad-core 64-bit ARM
®
Cortex
®
-A53, the Intel Stratix 10 SoC devices deliver power efficient, application-class
processing and allow designers to extend hardware virtualization into the FPGA fabric.
Intel Stratix 10 SoC devices demonstrate Intel's commitment to high-performance
SoCs and extend Intel's leadership in programmable devices featuring an ARM-based
processor system.
Important innovations in Intel Stratix 10 FPGAs and SoCs include:
All new HyperFlex core architecture delivering 2X the core performance compared
to previous generation high-performance FPGAs
Industry leading Intel 14-nm Tri-Gate (FinFET) technology
Heterogeneous 3D System-in-Package (SiP) technology
Monolithic core fabric with up to 5.5 million logic elements (LEs)
Up to 96 full duplex transceiver channels on heterogeneous 3D SiP transceiver
tiles
Transceiver data rates up to 28.3 Gbps chip-to-chip/module and backplane
performance
M20K (20 kbit) internal SRAM memory blocks
Fractional synthesis and ultra-low jitter LC tank based transmit phase locked loops
(PLLs)
Hard PCI Express
®
Gen3 x16 intellectual property (IP) blocks
Hard 10GBASE-KR/40GBASE-KR4 Forward Error Correction (FEC) in every
transceiver channel
Hard memory controllers and PHY supporting DDR4 rates up to 2666 Mbps per pin
Hard fixed-point and IEEE 754 compliant hard floating-point variable precision
digital signal processing (DSP) blocks with up to 10 TFLOPS compute performance
with a power efficiency of 80 GFLOPS per Watt
Quad-core 64-bit ARM Cortex-A53 embedded processor running up to 1.5 GHz in
SoC family variants
Programmable clock tree synthesis for flexible, low power, low skew clock trees
S10-OVERVIEW | 2018.08.08
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