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DD8C32_64x64A.fm - Rev. J 8/08 EN
11 ©2003 Micron Technology, Inc. All rights reserved.
256MB, 512MB (x64, SR) 184-Pin DDR SDRAM UDIMM
Electrical Specifications
Table 10: IDD Specifications and Conditions – 256MB (All Other Die Revisions)
Values are shown for the MT46V32M8 DDR SDRAM only and are computed from values specified in the
256Mb (32 Meg x 8) component data sheet
Parameter/Condition Symbol -40B -335 -262
-26A/
-265
Units
Operating one bank active-precharge current:
t
RC =
t
RC (MIN);
t
CK =
t
CK (MIN); DQ, DM, and DQS inputs changing once per clock
cycle; Address and control inputs changing once every two clock
cycles
IDD0 1,080 1,000 1,000 960 mA
Operating one bank active-read-precharge current: BL = 4;
t
RC =
t
RC (MIN);
t
CK =
t
CK (MIN); IOUT = 0mA; Address and control
inputs changing once per clock cycle
IDD1 1,360 1,360 1,280 1,160 mA
Precharge power-down standby current: All device banks idle;
Power-down mode;
t
CK =
t
CK (MIN); CKE = LOW
IDD2P 32 32 32 32 mA
Idle standby current: CS# = HIGH; All device banks idle;
t
CK =
t
CK (MIN); CKE = HIGH; Address and other control inputs
changing once per clock cycle; V
IN
= V
REF
for DQ, DM, and DQS
IDD2F 480 400 360 360 mA
Active power-down standby current: One device bank active;
Power-down mode;
t
CK =
t
CK (MIN); CKE = LOW
IDD3P 320 240 200 200/
240
mA
Active standby current: CS# = HIGH; CKE = HIGH; One device bank
active;
t
RC =
t
RAS (MAX);
t
CK =
t
CK (MIN); DQ, DM, and DQS inputs
changing twice per clock cycle; Address and other control inputs
changing once per clock cycle
IDD3N 560 480 400 400 mA
Operating burst read current: BL = 2; Continuous burst reads; One
device bank active; Address and control inputs changing once per
clock cycle;
t
CK =
t
CK (MIN); IOUT = 0mA
IDD4R 1,600 1,400 1,200 1,200 mA
Operating burst write current: BL = 2; Continuous burst writes;
One device bank active; Address and control inputs changing once
per clock cycle;
t
CK =
t
CK (MIN); DQ, DM, and DQS inputs changing
twice per clock cycle
IDD4W 1,560 1,400 1,200 1,200 mA
Auto refresh current
t
REFC =
t
RC (MIN)
IDD5 2,080 2,040 1,880 1,880/
1,960
mA
t
REFC = 7.8125µs
IDD5A 48 48 48 48 mA
Self refresh current: CKE ≤ 0.2V
IDD632323232mA
Operating bank interleave read current: Four device bank
interleaving reads; BL = 4 with auto precharge:
t
RC =
t
RC (MIN);
t
CK =
t
CK (MIN); Address and control inputs change only during
active READ or WRITE commands
IDD7 3,760 3,280 2,800 2,800/
2,920
mA
