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Table 5. INPUT/OUTPUT TABLE
ENA ENB INA INB
NCP81071A NCP81071B NCP81071C
OUTA OUTB OUTA OUTB OUTA OUTB
H H L L H H L L H L
H H L H H L L H H H
H H H L L H H L L L
H H H H L L H H L H
L L Any Any L L L L L L
Any Any x (Note 1) x (Note 1) L L L L L L
x (Note 1) x (Note 1) L L H H L L H L
x (Note 1) x (Note 1) L H H L L H H H
x (Note 1) x (Note 1) H L L H H L L L
x (Note 1) x (Note 1) H H L L H H L H
1. Floating condition, internal resistive pull up or pull down configures output condition
PRODUCT MATRIX
NCP81071A NCP81071B NCP81071C
NCP81071
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Table 6. ELECTRICAL CHARACTERISTICS
(Typical values: V
DD
=12 V, 1 mF from V
DD
to GND, T
A
= T
J
= −40°C to 140°C, typical at T
AMB
= 25°C, unless otherwise specified)
Parameter
Symbol Test Conditions Min Typ Max Units
SUPPLY VOLTAGE
VDD Under Voltage Lockout (rising) V
CCR
VDD rising 3.5 4.0 4.5 V
VDD Under Voltage Lockout
(hysteresis)
V
CCH
400 mV
Operating Current (no switching) I
DD
INA = 0, INB = 5 V, ENA = ENB = 0
INA = 5 V, INB = 0, ENA = ENB = 0
INA = 0, INB = 5 V, ENA = ENB = 5 V
INA = 5 V, INB = 0, ENA = ENB = 5 V
1.4 3 mA
VDD Under Voltage Lockout to Output
Delay (Note 2)
VDD rising 10
ms
INPUTS
High Threshold
V
thH
Input rising from logic low 1.8 2.0 2.2 V
Low Threshold V
thL
Input falling from logic high 0.8 1.0 1.2 V
INA, INB Pull−Up Resistance OUTA = OUTB = Inverter Configuration 200
kW
INA, INB Pull−Down Resistance OUTA = OUTB = Buffer Configuration 200
kW
OUTPUTS
Output Resistance High
R
OH
IOUT = −10 mA 0.8 2
W
Output Resistance Low R
OL
IOUT = +10 mA 0.8 2
W
Peak Source Current (Note 3) I
Source
OUTA/OUTB = GND
200 ns Pulse
5 A
Miller Plateau Source Current (Note 3) I
Source
OUTA/OUTB = 5.0 V
200 ns Pulse
4.5 A
Peak Sink Current (Note 3) I
Sink
OUTA/OUTB = VDD
200 ns Pulse
5 A
Miller Plateau Sink Current (Note 3) I
Sink
OUTA/OUTB = 5.0 V
200 ns Pulse
3.5 A
ENABLE
High−Level Input Voltage
V
IN_H
Low to High Transition 1.8 2.0 2.2 V
Low−Level Input Voltage V
IN_L
High to Low Transition 0.8 1.0 1.2 V
ENA, ENB pull−up resistance 200
kW
Propagation Delay Time (EN to OUT)
(Notes 2, 4)
t
d3
C
Load
= 1.8 nF 16 20 29 ns
Propagation Delay Time (EN to OUT)
(Notes 2, 4)
t
d4
C
Load
= 1.8 nF 16 20 29 ns
SWITCHING CHARACTERISTICS
Propagation Delay Time Low to High,
IN Rising (IN to OUT) (Notes 2, 4)
t
d1
C
Load
= 1.8 nF 16 20 29 ns
Propagation Delay Time High to Low,
IN Falling (IN to OUT) (Notes 2, 4)
t
d2
C
Load
= 1.8 nF 16 20 29 ns
Rise Time (Note 4) t
r
C
Load
= 1.8 nF 8 15 ns
Fall Time (Note 4) t
f
C
Load
= 1.8 nF 8 15 ns
Delay Matching between 2 Channels
(Note 5)
t
m
INA = INB, OUTA and OUTB at 50%
Transition Point
1 4 ns
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2. Guaranteed by design.
3. Not production tested, guaranteed by design and statistical analysis.
4. See timing diagrams in Figure 2, Figure 3, Figure 4 and Figure 5.
5. Guaranteed by characterization.
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t
d3
t
d4
Input
Enable
Output
2 V
2 V
1 V
1 V
90%
10%
t
d3
t
d4
Input
Enable
Output
2 V
2 V
1 V
1 V
90%
10%
Figure 2. Enable Function for
Non−inverting Input Driver Operation
Figure 3. Enable Function for Inverting
Input Driver Operation
t
d1
t
d2
Input
Enable
Output
2 V
2 V
1 V
1 V
90%
10%
t
r
t
f
t
d1
t
d2
Input
Enable
Output
2 V
2 V
1 V
1 V
90%
10%
Figure 4. Non−inverting Input Driver Operation Figure 5. Inverting Input Driver Operation

NCP81071AMNTXG

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Gate Drivers DUAL LOW-SIDE DRIVER
Lifecycle:
New from this manufacturer.
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