IDT8N3Q001 REV G Data Sheet QUAD-FREQUENCY PROGRAMMABLE-XO
IDT8N3Q001GCD REVISION A
MARCH 6, 2012
11 ©2012 Integrated Device Technology, Inc.
Termination for 3.3V LVPECL Outputs
The clock layout topology shown below is a typical termination for
LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
The differential outputs are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must be
used for functionality. These outputs are designed to drive 50
transmission lines. Matched impedance techniques should be used
to maximize operating frequency and minimize signal distortion.
Figures 1A and 1B show two different layouts which are
recommended only as guidelines. Other suitable clock layouts may
exist and it would be recommended that the board designers
simulate to guarantee compatibility across all printed circuit and clock
component process variations.
Figure 1A. 3.3V LVPECL Output Termination Figure 1B. 3.3V LVPECL Output Termination
3.3V
V
CC
- 2V
R1
50Ω
R2
50Ω
RTT
Z
o
= 50Ω
Z
o
= 50Ω
+
_
RTT = * Z
o
1
((V
OH
+ V
OL
) / (V
CC
– 2)) – 2
3.3V
LVPECL
Input
R1
84Ω
R2
84Ω
3.3V
R3
125Ω
R4
125Ω
Z
o
= 50Ω
Z
o
= 50Ω
LVPECL Inp
3.3V
.3V
+
_
