LTC5587
10
5587f
PIN FUNCTIONS
SDO (Pin 1): Three-State Serial Data Output. The A/D
conversion result is shifted out on SDO as a serial data
stream with MSB first. The data stream consists of 12 bits
of conversion data followed by trailing zeros.
SCK (Pin 2): Shift Clock Input. The SCK serial clock syn-
chronizes the serial data transfer. SDO data transitions
on the falling edge of SCK.
OV
DD
(Pin 3): ADC Output Driver Supply Voltage, 1.0V
to 3.6V. OV
DD
should be bypassed with a 1µF ceramic
capacitor. OV
DD
can be driven separately from V
DD
and
OV
DD
can be higher than V
DD
.
V
OUT
(Pin 4): Detector Analog Voltage Output. An internal
series 300Ω resistor at the detector output allows for
simple R-C filtering with a capacitor placed on this pin to
GND. A 1000pF capacitor is recommended for a corner
frequency of 500kHz.
C
SQ
(Pin 6): Optional low-frequency range extension
capacitor for frequencies below 250MHz. Connect 0.01µF
from this pin to ground for 10MHz operation.
RF (Pin 7): RF Input Voltage. Should be externally
DC-blocked. A capacitor of 1000pF is recommended. This
pin has an internal 205Ω termination.
V
CC
(Pin 8): Detector Power Supply Voltage, 2.7V to 3.6V.
Can be connected to the V
DD
voltage supply. V
CC
should
be bypassed with a 1µF ceramic capacitor. If V
CC
and V
DD
are tied together, then bypass with 2.2µF.
EN (Pin 9): Detector Enable. A logic low or no-connect
on the enable pin shuts down the detector. A logic high
enables the detector. An internal 500k pull-down resistor
ensures the detector is off when the pin is left floating.
V
REF
(Pin 10): ADC Reference Input Voltage. V
REF
defines
the input span of the ADC, 0V to V
REF
. The V
REF
range
is 1.4V to V
DD
. Bypass to ground with a 1µF ceramic
capacitor.
V
DD
(Pin 11): ADC Power Supply Voltage, 2.7V to 3.6V.
V
DD
should be bypassed with a 1µF ceramic capacitor.
CONV (Pin 12): C o n v e r t I n p u t . T h i s a c t i v e h i g h s i g n a l s t a r t s
a conversion on the rising edge. The ADC automatically
powers down after conversion. A logic low on this input
enables the SDO pin, allowing the data to be shifted out.
GND (Pin 5, Exposed Pad Pin 13): Ground. For high-
frequency operation, backside ground connection should
have a low-inductance connection to the pcb ground using
many through-hole vias. See layout information.
BLOCK DIAGRAM
5587 BD
EXPOSED
PAD
V
OUT
SDO
V
DD
V
REF
GNDV
CC
ENC
SQ
OV
DD
RF
7
413
150kHz LPF
OUTPUT
BUFFER
300
RMS
DETECTOR
THREE-STATE
SERIAL OUTPUT
PORT
S/H
12-BIT ADC
11
10896
3
1
SCK
2
CONV
12
TIMING
LOGIC
BIAS
5
