288 Pin DDR4 1.2V 2400 ECC UDIMM
4GB Based on 512Mx8
AQD-D4U4GE24-SG
Advantech
13
1
69 Connector to SRAM bit mapping CB4 - 7 36
70 Connector to SRAM bit mapping DQ32 - 35 16
71 Connector to SRAM bit mapping DQ36 - 39 36
72 Connector to SRAM bit mapping DQ40 - 43 16
73 Connector to SRAM bit mapping DQ44 - 47 36
74 Connector to SRAM bit mapping DQ48 - 51 16
75 Connector to SRAM bit mapping DQ52 - 55 36
76 Connector to SRAM bit mapping DQ56 - 59 16
77 Connector to SRAM bit mapping DQ60 - 63 36
78~116 Reserved — 00
117
Fine offset for minimum CAS to CAS delay time (tCCD_L min),
same bank group
5ns 00
118
Fine offset for minimum activate to activate delay time (tRRD_L min),
same bank group
4.9ns 9C
119
Fine offset for minimum activate to activate delay time (tRRD_S min),
different e bank group
3.3ns B5
120 Fine offset for minimum activate to activate/refresh delay time(tRC min) 45.75ns 00
121 Fine offset for minimum ROW precharge delay time (tRP min) 13.75ns 00
122 Fine offset for minimum RAS to CAS delay time(tRCD min) 13.75ns 00
123 Fine offset for minimum CAS latency time (tAA min) 13.75ns 00
124 Fine offset for SDRAM maximum cycle time(tCKAVG max) 1.6ns E7
125 Fine offset for SDRAM minimum cycle time(tCKAVG min) 0.833ns D6
126 CRC for base configuration section section, Least significant byte F9 F9
127 CRC for base configuration section section, Most significant byte C1 C1
128 Raw card extension, module nominal height R/C D, 31.25mm 11
129 Module maximum thickenss 1 < thickness ≤ 2mm 11
130 Reference raw card used Row Card D 03
131 Address mapping from edge connector to DRAM Standard = 0 00
132~253 Reserved — 00
254 CRC for base configuration section section, Least significant byte E7 E7
255 CRC for base configuration section section, Most significant byte AF AF
256-319 Reserved — 00
