7
FN6174.2
May 29, 2012
Power-On Reset (POR)
Applying power to the ISL88001, ISL88002, ISL88003
activates a POR circuit, which asserts reset once V
DD
= 1 V.
(i.e. RST
goes LOW). This provides several benefits:
• It prevents the system microprocessor from starting to
operate with insufficient voltage.
• It prevents the processor from operating prior to
stabilization of the oscillator.
• It ensures that the monitored device is held out of
operation until internal registers are properly loaded.
• It allows time for an FPGA to download its configuration
prior to initialization of the circuit.
The reset signal remains asserted until V
DD
rises above the
minimum voltage sense level for time period t
POR
. This
ensures that the V
DD
voltage has stabilized.
Optional V
DD
de-coupling capacitance can be added to filter
transients if needed.
See Figures 13 and 14 illustrating the available evaluation
platform, ISL88001/2/3EVAL1Z. This evaluation board is
shipped with the many released variants loosely packed and
the 4.6V threshold variants mounted for immediate
evaluation.
FIGURE 2. VOLTAGE MONITORING TIMING DIAGRAM
V
DD
V
TH/
V
POR
1V
RST
t
POR
t
POR
t
RPD
Parametric Performance
FIGURE 3. ISL88001 RST t
POR
~144ms
FIGURE 4. ISL88002 RST
t
POR
~155ms, R
PU
= 5kΩ
ISL88001, ISL88002, ISL88003
