2-OUTPUT 3.3V PCIE ZERO-DELAY BUFFER 4 FEBRUARY 8, 2017
9DBL0242 / 9DBL0252 DATASHEET
Test Loads
Alternate Terminations
The 9DBL family can easily drive LVPECL, LVDS, and CML logic. See “AN-891 Driving LVPECL, LVDS, and CML Logic with
IDT's "Universal" Low-Power HCSL Outputs” for details.
Terminations
Device Zo ()Rs ()
9DBL0242 100 None needed
9DBL0252 100 7.5
9DBL02P2 100 Prog.
9DBL0242 85 N/A
9DBL0252 85 None needed
9DBL02P2 85 Prog.
FEBRUARY 8, 2017 5 2-OUTPUT 3.3V PCIE ZERO-DELAY BUFFER
9DBL0242 / 9DBL0252 DATASHEET
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the 9DBL0242 / 9DBL0252. These ratings, which are
standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other
conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the
recommended operating temperature range.
Electrical Characteristics–Clock Input Parameters
Electrical Characteristics–SMBus Parameters
PARAMETER SYMBOL CONDITIONS
MIN TYP MAX
UNITS NOTES
Supply Voltage VDDx 4.6 V 1,2
Input Voltage V
IN
-0.5 V
DD
+0.5 V 1,3
Input High Voltage, SMBus V
IHSMB
SMBus clock and data pins 3.9 V 1
Storage Temperature Ts -65 150 °C 1
Junction Temperature Tj 125 °C 1
Input ESD protection
ESD prot Human Body Model 2500 V 1
1
Guaranteed by design and characterization, not 100% tested in production.
2
Operation under these conditions is neither implied nor guaranteed.
3
Not to exceed 4.6V.
TA = T
AMB,
Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Input Crossover Voltage -
DIF_IN
V
CROSS
Cross Over Voltage 150 900 mV 1
Input Swing - DIF_IN V
SWING
Differential value 300 mV 1
Input Slew Rate - DIF_IN dv/dt Measured differentially 0.4 8 V/ns 1,2
Input Leakage Current I
IN
V
IN
= V
DD ,
V
IN
=
GND -5 5 uA
Input Duty Cycle d
tin
Measurement from differential wavefrom 45 55 % 1
Input Jitter - Cycle to Cycle J
DIFIn
Differential Measurement 0 125 ps 1
1
Guaranteed by design and characterization, not 100% tested in production.
2
Slew rate measured through +/-75mV window centered around differential zero
TA = T
AMB;
Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
SMBus Input Low Voltage V
ILSMB
V
DDSMB
= 3.3V 0.8 V
SMBus Input High Voltage V
IHSMB
V
DDSMB
= 3.3V 2.1 3.6 V
SMBus Output Low Voltage V
OLSMB
@ I
PULLUP
0.4 V
SMBus Sink Current I
PULLUP
@ V
OL
4mA
Nominal Bus Voltage V
DDSMB
2.7 3.6 V
SCLK/SDATA Rise Time t
RSMB
(Max VIL - 0.15) to (Min VIH + 0.15) 1000 ns 1
SCLK/SDATA Fall Time t
FSMB
(Min VIH + 0.15) to (Max VIL - 0.15) 300 ns 1
SMBus Operating
Frequency
f
SMB
SMBus operating frequency 500 kHz 2,3
1
Guaranteed by design and characterization, not 100% tested in production.
2.
The device must be powered up for the SMBus to function.
3.
The differential input clock must be running for the SMBus to be active
2-OUTPUT 3.3V PCIE ZERO-DELAY BUFFER 6 FEBRUARY 8, 2017
9DBL0242 / 9DBL0252 DATASHEET
Electrical Characteristics–Input/Supply/Common Parameters–Normal Operating
Conditions
TA = T
AMB,
Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Supply Voltage VDDx Supply voltage for core and analog 3.135 3.3 3.465 V
Ambient Operating
Temperature
T
AMB
Industrial range -40 25 85 °C
Input High Voltage V
IH
0.75 V
DDx
V
DDx
+ 0.3 V
Input Low Voltage V
IL
-0.3 0.25 V
DDx
V
Input High Voltage V
IHtri
0.75 V
DDx
V
DD
+ 0.3 V
Input Mid Voltage V
IMtri
0.4 V
DDx
0.5 V
DDx
0.6 V
DDx
V
Input Low Voltage V
ILtri
-0.3 0.25 V
DDx
V
I
IN
Single-ended inputs, V
IN
= GND, V
IN
= VDD -5 5 uA
I
INP
Single-ended inputs
V
IN
= 0 V; Inputs with internal pull-up resistors
V
IN
= VDD; Inputs with internal pull-down resistors
-50 50 uA
Bypass mode 1 200 MHz 2
100MHz PLL mode 60 100.00 140 MHz 2
50MHz PLL mode 30 50.00 65 MHz 2
125MHz PLL mode 75 125.00 175 MHz 2
Pin Inductance L
p
in
7nH1
C
IN
Logic Inputs, except DIF_IN 1.5 5 pF 1
C
INDIF_I N
DIF_IN differential clock inputs 1.5 2.7 pF 1
C
OU
T
Output pin capacitance 6 pF 1
Clk Stabilization T
STAB
From V
DD
Power-Up and after input clock
stabilization or de-assertion of PD# to 1st clock
1ms1,2
Input SS Modulation
Frequency PCIe
f
MODINPCIe
Allowable Frequency for PCIe Applications
(Triangular Modulation)
30 33 kHz
Input SS Modulation
Frequency non-PCIe
f
MODIN
Allowable Frequency for non-PCIe Applications
(Triangular Modulation)
066kHz
OE# Latency t
LATOE#
DIF start after OE# assertion
DIF stop after OE# deassertion
1 3 clocks 1,3
Tdrive_PD# t
DRVPD
DIF output enable after
PD# de-assertion
300 us 1,3
Tfall t
F
Fall time of single-ended control inputs 5 ns 2
Trise t
R
Rise time of single-ended control inputs 5 ns 2
1
Guaranteed by design and characterization, not 100% tested in production.
2
Control input must be monotonic from 20% to 80% of input swing.
3
Time from deassertion until outputs are >200 mV
Capacitance
Input Frequency F
IN
Input Current
Single-ended inputs, except SMBus
Single-ended tri-level inputs ('_tri' suffix)

9DBL0242BKILF

Mfr. #:
Manufacturer:
IDT
Description:
Clock Buffer 2 O/P 3.3V PCIE ZERO DELAY BUF
Lifecycle:
New from this manufacturer.
Delivery:
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