17
COMMERCIAL TEMPERATURE RANGE
IDT72V3683/72V3693/72V36103 3.3V CMOS SyncFIFO
TM
WITH
BUS-MATCHING 16,384 x 36, 32,768 x 36 and 65,536 x 36
Figure 6. Serial Programming of the Almost-Full Flag and Almost-Empty Flag Offset Values after Reset
(IDT Standard and FWFT Modes)
NOTE:
1. CSA = LOW, W/RA = HIGH, MBA = LOW.
Figure 5. Parallel Programming of the Almost-Full Flag and Almost-Empty Flag Offset Values after Reset
(IDT Standard and FWFT Modes)
NOTES:
1. It is not necessary to program offset register bits on consecutive clock cycles. FIFO write attempts are ignored until FF/IR is set HIGH.
2. Programmable offsets are written serially to the SD input in the order AF offset (Y) and AE offset (X).
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CLKA
RS1
FF/IR
A0-A35
FS1,FS0
ENA
t
FSH
t
WFF
t
ENH
t
ENS2
t
DS
t
DH
4
0,0
AF Offset
Y
AE Offset
(X)
First Word to FIFO1
t
FSH
t
FSS
FS2
t
FSS
1
2
CLKA
FF/IR
t
SENS
t
SENH
FS0/SD
(2)
t
SPH
t
SENS
t
SENH
t
FSS
t
WFF
FS1/SEN
AE Offset
X
LSB
t
SDS
t
SDH
t
SDS
t
SDH
AF Offset
Y
MSB
RS1
4
t
FSS
t
FSH
FS2
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