74AHC_AHCT164_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 1 — 5 July 2013 9 of 19
NXP Semiconductors 74AHC164-Q100; 74AHCT164-Q100
8-bit serial-in/parallel-out shift register
[1] Typical values are measured at nominal supply voltage (V
CC
= 3.3 V and V
CC
= 5.0 V).
[2] t
pd
is the same as t
PLH
and t
PHL
.
[3] t
pd
is the same as t
PHL
only.
[4] C
PD
is used to determine the dynamic power dissipation (P
D
in W).
P
D
=C
PD
V
CC
2
f
i
N+(C
L
V
CC
2
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in V;
N = number of inputs switching;
(C
L
V
CC
2
f
o
) = sum of the outputs.
t
rec
recovery
time
MR to CP; see Figure 8
V
CC
= 3.0 V to 3.6 V 2.5 - - 2.5 - 2.5 - ns
V
CC
= 4.5 V to 5.5 V 2.5 - - 2.5 - 2.5 - ns
C
PD
power
dissipation
capacitance
f
i
= 1 MHz; V
I
=GNDtoV
CC
[4]
-48- - - - -pF
74AHCT164-Q100; V
CC
= 4.5 V to 5.5 V
t
pd
propagation
delay
CP to Qn; see Figure 7
[2]
C
L
= 15 pF - 3.4 9.0 1.0 10.5 1.0 11.5 ns
C
L
= 50 pF - 4.9 11.0 1.0 12.5 1.0 14.0 ns
MR
to Qn; see Figure 8
[3]
C
L
= 15 pF - 3.5 8.6 1.0 10.0 1.0 11.0 ns
C
L
= 50 pF - 5.0 10.6 1.0 12.0 1.0 13.5 ns
f
max
maximum
frequency
see Figure 7
C
L
= 15 pF 125 175 - 105 - 85 - MHz
C
L
= 50 pF 85 115 - 75 - 65 - MHz
t
W
pulse width CP HIGH or LOW;
see Figure 7
5.0 - - 5.0 - 5.0 - ns
t
WL
pulse width
LOW
MR; see Figure 8 5.0 - - 5.0 - 5.0 - ns
t
su
set-up time DSA, DSB to CP;
see Figure 9
4.5 - - 4.5 - 4.5 - ns
t
h
hold time DSA, DSB to CP;
see Figure 9
2.0 - - 2.0 - 2.0 - ns
t
rec
recovery
time
MR to CP; see Figure 8 2.5 - - 2.5 - 2.5 - ns
C
PD
power
dissipation
capacitance
f
i
= 1 MHz; V
I
=GNDtoV
CC
[4]
-51- - - - -pF
Table 7. Dynamic characteristics
…continued
Voltages are referenced to GND (ground = 0 V); for test circuit, see Figure 10.
Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit
Min Typ
[1]
Max Min Max Min Max
