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TEA1755LT/1Y

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P35
TEA1755LT All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 1.1 — 13 March 2015 10 of 35
NXP Semiconductors
TEA1755LT
HV start-up DCM/QR flyback controller with integrated DCM/QR PFC
controller
(1)
The voltage is limited to V
start(soft)PFC
.
The start level and time constant of the increasing primary current level is externally
adjusted by changing the R
SS1
and C
SS1
values.
(2)
The charging current I
start(soft)PFC
flows while the PFCSENSE pin voltage is < 0.5 V. If
V
PFCSENSE
exceeds 0.5 V, the soft-start current source starts limiting current I
start(soft)PFC
.
When the PFC starts switching, the I
start(soft)PFC
current source is switched off; see
Figure 5
.
7.2.6 PFC switch on/switch off control
When the flyback converter output power (see Section 7.3) is low, the flyback converter
switches to FR mode. When the switching frequency of the flyback in
FR mode < f
sw(fb)swoff(PFC)
(53 kHz), the PFC circuit is switched off to maintain high
efficiency. Connect a capacitor to the PFCTIMER pin (see Section 7.2.7
) to delay the PFC
switching off.
During low-power mode operation, the PFCCOMP pin is clamped to a minimum voltage of
3.32 V or 1.92 V and a maximum voltage of 3.75 V. The lower clamp voltage depends on
V
VINSENSE
. This voltage limits the maximum power that is delivered when the PFC is
switched on again. The upper clamp voltage ensures that the PFC returns from low-power
mode to its normal regulation point in a limited time.
In FR mode, when the flyback converter switching frequency exceeds
f
sw(fb)swon(PFC)
(73 kHz), the PFC circuit is switched on. If the flyback converter duty cycle
is > 50 % or V
FBCTRL
is > 3.75 V, the PFC circuit is also switched on.
7.2.7 PFC switch off delay (PFCTIMER pin)
When the flyback converter switching frequency in FR mode is < f
sw(fb)swoff(PFC)
(53 kHz),
the IC then outputs a 4.7 A current to the PFCTIMER pin. When V
PFCTIMER
reaches 3 V,
the PFC is switched off by performing a soft-stop.
Fig 5. Soft-start of the PFC
V
PFCSEN SE
I
start softPFC
R
SS1
=
soft s– tart 3 R
SS1
C
SS1
=
TEA1755LT All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 1.1 — 13 March 2015 11 of 35
NXP Semiconductors
TEA1755LT
HV start-up DCM/QR flyback controller with integrated DCM/QR PFC
controller
A switch discharges the PFCTIMER pin capacitor when the flyback controller operating
frequency is > f
sw(fb)swon(PFC)
(73 kHz). At the same moment, the PFC stage is also
switched on.
Connect a capacitor to the PFCTIMER pin (see Section 7.2.7
) to prevent the PFC from
switching off due to a dynamic load that leads to repetitive crossing of f
sw(fb)swoff(PFC)
and
f
sw(fb)swon(PFC)
. A 1 nF minimum capacitor value is recommended to prevent noise
influencing the PFC switch on/ switch off behavior.
The PFCTIMER pin capacitor is also discharged when the flyback maximum switching
frequency is higher than 53 kHz. This feature prevents PFC on/off toggling during
dynamic loads causing the flyback to operate repetitively near f
sw(fb)swoff(PFC)
and
f
sw(fb)swon(PFC)
.
It is also possible to control PFC switch-on and switch off externally. When V
PFCTIMER
is
driven below 1.03 V, the PFC stage is on. When the PFCTIMER pin voltage is driven
above 4.4 V, the PFC stage is switched off. The external control overrides the PFC stage
control by the flyback controller (see Figure 6
).
The PFCTIMER pin has an internal clamp circuit starting around 10 V with a current
capability of 0.1 mA
7.2.8 Dual-boost PFC
The mains input voltage modulates the PFC output voltage. The mains input voltage is
measured using the VINSENSE pin. If V
VINSENSE
< 2.28 V, the current is sourced from the
VOSENSE pin. To ensure switch-over is stable, the current reaches its absolute maximum
value for V
VINSENSE
< 2.08 V, see Figure 7.
At low VINSENSE input voltages, the output current is 8.1 A. This output current, in
combination with the resistors on the VOSENSE pin, sets the lower PFC output voltage
level at low mains voltages. At high mains input voltages, the current is switched to zero.
The PFC output voltage is then at its maximum. As this current is zero in this situation, it
does not affect the accuracy of the PFC output voltage.
To ensure a correct switch-off of the application, the VOSENSE current switches to its
maximum value of 8.1 A when V
VOSENSE
drops below 2.1 V.
Fig 6. PFC switch on and switch off using the PFCTIMER pin
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TEA1755LT All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 1.1 — 13 March 2015 12 of 35
NXP Semiconductors
TEA1755LT
HV start-up DCM/QR flyback controller with integrated DCM/QR PFC
controller
7.2.9 Overcurrent protection (PFCSENSE pin)
The maximum peak current is limited cycle-by-cycle by sensing the voltage across an
external sense resistor, R
SENSE1
, on the source of the external MOSFET. The voltage is
measured using the PFCSENSE pin.
7.2.10 Mains undervoltage lockout/brownout protection (VINSENSE pin)
To prevent the PFC from operating at very low mains input voltages, V
VINSENSE
is sensed
continuously. When V
VINSENSE
drops below the V
stop(VINSENSE)
level, switching of the PFC
is stopped.
7.2.11 Overvoltage protection (VOSENSE pin)
To prevent output overvoltage during load steps and mains transients, an overvoltage
protection circuit is built in.
When V
VOSENSE
exceeds the V
OVP(VOSENSE)
level, switching of the PFC circuit is
prevented. Switching of the PFC restarts when the VOSENSE pin voltage drops below the
V
OVP(VOSENSE)
level again.
OVP is also triggered when the resistor between the VOSENSE pin and ground is open.
7.2.12 PFC open-loop protection (VOSENSE pin)
The PFC circuit does not start switching until the V
VOSENSE
pin is greater than the
V
th(ol)(VOSENSE)
level. This feature protects the application from open-loop and VOSENSE
short-circuit situations.
7.2.13 Driver (PFCDRIVER pin)
The driver circuit to the gate of the power MOSFET has a current sourcing capability of
500 mA at 2 V on the PFCDRIVER pin and a current sink capability of 1.2 A at 10 V on the
PFCDRIVER pin. These capabilities ensure fast switch-on and switch-off of the power
MOSFET for efficient operation.
7.3 Flyback controller
The TEA1755LT includes a controller for a flyback converter. The flyback converter
operates in quasi-resonant, discontinuous conduction mode or burst mode with valley
switching. The auxiliary winding of the flyback transformer provides demagnetization
detection and powers the IC after start-up.
Fig 7. Voltage to current transfer function for dual-boost PFC
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P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P35

TEA1755LT/1Y

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Manufacturer:
NXP Semiconductors
Description:
AC/DC Converters TEA1755LT/SO16//1/REEL 13 Q1 DP
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