www.vishay.com Document Number: 91052
4 S11-1048-Rev. C, 30-May-11
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
IRF740AS, SiHF740AS, IRF740AL, SiHF740AL
Vishay Siliconix
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage
Fig. 7 - Typical Source-Drain Diode Forward Voltage
Fig. 8 - Maximum Safe Operating Area
1
10
10 10
2
C, Capacitance (pF)
V
DS
,
Drain-to-Source Voltage (V)
C
iss
C
rss
C
oss
V
GS
= 0 V, f = 1 MHz
C
iss
= C
gs
+ C
gd
, C
ds
Shorted
C
rss
= C
gd
C
oss
= C
ds
+ C
gd
91052_05
10
5
10
2
10
3
10
4
1
10
3
Q
G
, Total Gate Charge (nC)
V
GS
, Gate-to-Source Voltage (V)
20
16
12
8
0
4
04020 3010
V
DS
= 80 V
V
DS
= 200 V
For test circuit
see figure 13
V
DS
= 320 V
91052_06
I
D
= 10 A
10
2
10
V
SD
, Source-to-Drain Voltage (V)
I
SD
, Reverse Drain Current (A)
0.2
1.0
0.80.60.4
V
GS
= 0 V
91052_07
T
J
= 25 °C
T
J
= 150 °C
1
0.1
1.41.2
10 µs
100 µs
1 ms
10 ms
Operation in this area limited
by R
DS(on)
V
DS
, Drain-to-Source Voltage (V)
I
D
, Drain Current (A)
T
C
= 25 °C
T
J
= 150 °C
Single Pulse
10
2
1
10
10
10
2
10
3
91052_08
